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Proceedings ArticleDOI

Measuring Area-Complexity Using Boolean Difference

05 Jan 2013-pp 245-250
TL;DR: This paper demonstrates how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives using the theory of Boolean difference and Taylor expansion for Boolean functions.
Abstract: For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like literal count, number of primary input/outputs, etc. have been used in the past as area-complexity metrics. In this paper, we propose a novel area-complexity measure using the theory of Boolean difference and Taylor expansion for Boolean functions. We demonstrate how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives. We evaluate the metric on circuits from MCNC benchmark suite and a sizeable collection of randomly generated circuits. We compare our metric with existing techniques based on literal-count and BDD properties. We show that the new area-complexity measure is accurate within 10% of the actual number of gates synthesized using ABC as opposed to at least 100% and 15% for the metrics based on literal-count and BDD properties respectively. We also show the robustness of our metric across three different gate-libraries.
Citations
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Proceedings ArticleDOI
14 Mar 2016
TL;DR: A resource-aware functional patch generation approach by gate count and wiring cost estimations, which considers the physical location of the patch and a set of nearby spare cells and produces the patch with minimal wiring cost instead of minimal size.
Abstract: Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising.

10 citations

References
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Journal ArticleDOI
TL;DR: The complexity of an electronic switching circuit is defined in a sufficiently general way so that most definitions which are presently used may be included and theoretical bounds are compared with those obtained from a few known circuiit designs.
Abstract: The complexity of an electronic switching circuit is defined in a sufficiently general way so that most definitions which are presently used may be included. If ?(p, q) is the complexity of a p input q output circuit which has been minimized then we may define E(p, q) as the maximum of ?(p, q) over all p input, q output circuits. In spite of the generality of the definition of complexity one may obtain the following inequality which gives upper and lower bounds on this maximum complexity: C12r/r?E(p, q)?C22r/r where r = p+log2 q. In this expression C1 and C2 are constants independent of p and q which depend upon the definition of complexity. These theoretical bounds are compared with those obtained from a few known circuiit designs.

94 citations


"Measuring Area-Complexity Using Boo..." refers background in this paper

  • ...The switching activity was captured by the number of relay elements in the circuit....

    [...]

Proceedings ArticleDOI
24 Jun 1990
TL;DR: Experimental data is presented in support of the entropy definition of computational work based upon the input-output description of a Boolean function and circuit delay is shown to have a non-linear relationship to the computational work.
Abstract: Entropy measures are examined in view of the current logic synthesis methodology. The complexity of a Boolean function can be expressed in terms of computational work. Experimental data are presented in support of the entropy definition of computational work based upon the input-output description of a Boolean function. These data show a linear relationship between the computational work and the average number of literals in a multilevel implementation. The investigation includes single-output and multioutput function with and without don't care states. The experiments conducted on a large number of randomly generated functions showed that the effect of don't cares is to reduce the computational work. For several finite state machine benchmarks, the computational work gave a good estimate of the size of the circuit. Circuit delay is shown to have a nonlinear relationship to the computational work. >

65 citations


"Measuring Area-Complexity Using Boo..." refers background in this paper

  • ...Usage of number of literals in the Boolean equation (literal-count) as a measure of area-complexity was proposed in [3]....

    [...]

Journal ArticleDOI
TL;DR: Algebraic equations relating the classical concepts of prime implicants and of the discrete Fourier transform of a Boolean function to the differential operators are derived.
Abstract: After a brief outline of classical concepts relative to Boolean differential calculus, a theoretical study of the main differential operators is undertaken. Algebraic equations relating the classical concepts of prime implicants and of the discrete Fourier transform of a Boolean function to the differential operators are derived. Application of these concepts to several important problems arising in switching practice is mentioned.

61 citations

Proceedings ArticleDOI
19 Apr 1991
TL;DR: The authors have tested their layout models on the widely used elliptic-filter benchmark and show that these models can more accurately predict layout areas than models based on the number and size of registers and multiplexers.
Abstract: The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for macrocells (PLAs), the proposed models formulate layout area as a function of transistors and routing tracks which can be computed in O(n log n) time complexity, where n is the number of nets in the netlist. This allows one to explore design space in high-level synthesis rapidly and efficiently. The authors have tested their layout models on the widely used elliptic-filter benchmark. The results show that these models can more accurately predict layout areas than models based on the number and size of registers and multiplexers. >

48 citations


"Measuring Area-Complexity Using Boo..." refers background in this paper

  • ...For larger circuits, the area predicted was exponentially high while the circuit required much less gates....

    [...]

Journal ArticleDOI
TL;DR: Since ROBDD complexity can be predicted without building it, a great reduction in terms of time complexity for VLSI CAD designs can be achieved and very useful clues to tackle ROBDD optimization problems in the design of digital circuits can also be obtained.

20 citations


"Measuring Area-Complexity Using Boo..." refers methods in this paper

  • ...With rising popularity of BDDs in the 1990’s, many metrics used the structural parameters of the BDDs, like the number of nodes, as an area-complexity measure [7], [8]....

    [...]