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Proceedings ArticleDOI

Measuring Area-Complexity Using Boolean Difference

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TLDR
This paper demonstrates how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives using the theory of Boolean difference and Taylor expansion for Boolean functions.
Abstract
For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like literal count, number of primary input/outputs, etc. have been used in the past as area-complexity metrics. In this paper, we propose a novel area-complexity measure using the theory of Boolean difference and Taylor expansion for Boolean functions. We demonstrate how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives. We evaluate the metric on circuits from MCNC benchmark suite and a sizeable collection of randomly generated circuits. We compare our metric with existing techniques based on literal-count and BDD properties. We show that the new area-complexity measure is accurate within 10% of the actual number of gates synthesized using ABC as opposed to at least 100% and 15% for the metrics based on literal-count and BDD properties respectively. We also show the robustness of our metric across three different gate-libraries.

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Citations
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Proceedings ArticleDOI

Resource-aware functional ECO patch generation

TL;DR: A resource-aware functional patch generation approach by gate count and wiring cost estimations, which considers the physical location of the patch and a set of nearby spare cells and produces the patch with minimal wiring cost instead of minimal size.
References
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Journal Article

Linking Register-Transfer and Physical Levels of Design (Special Issue on Synthesis and Verification of Hardware Design)

TL;DR: A new layout model is proposed which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process.

Linking register-transfer and physical levels of design

TL;DR: Kurdahi et al. as discussed by the authors proposed a layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process.
Book

Progress in Applications of Boolean Functions

TL;DR: This book brings together five topics on the application of Boolean functions, and presents a tutorial view of new and emerging technologies in Boolean functions.
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