Measuring the Gap Between FPGAs and ASICs
01 Feb 2007-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 26, Iss: 2, pp 203-215
TL;DR: Experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic are presented.
Abstract: This paper presents experimental measurements of the differences between a 90-nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and, thereby, improve FPGAs. We describe the methodology by which the measurements were obtained and show that, for circuits containing only look-up table-based logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 35. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories. We find that these blocks reduce this average area gap significantly to as little as 18 for our benchmarks, and we estimate that extensive use of these hard blocks could potentially lower the gap to below five. The ratio of critical-path delay, from FPGA to ASIC, is roughly three to four with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 14 times and, with hard blocks, this gap generally becomes smaller
Citations
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22 Feb 2006
TL;DR: Experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic are presented.
Abstract: This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed hoices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power onsumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.
635 citations
Cites background or methods from "Measuring the Gap Between FPGAs and..."
...An early version of this paper appeared in [11]....
[...]
...In our past work, such settings were not used and the core-logic area gap was found to be 40 [11]....
[...]
Book•
02 Nov 2007
TL;DR: This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology.
Abstract: The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.
· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways
531 citations
01 Mar 2014
TL;DR: A new embeddable method for polyp detection in wireless capsule endoscopic images was developed and tested using boosting based approach that achieved good classification performance and can be implemented in situ with embedded hardware.
Abstract: Purpose
Wireless capsule endoscopy (WCE) is commonly used for noninvasive gastrointestinal tract evaluation, including the detection of mucosal polyps. A new embeddable method for polyp detection in wireless capsule endoscopic images was developed and tested.
491 citations
Cites background from "Measuring the Gap Between FPGAs and..."
...By considering the above state-of-the-art, the fact that an FPGA also consumes 12 times more dynamic power than an equivalent ASIC on average [31] and the power consumption of Virtex 5, we can estimate that the power consumption due to the processing will be approximatively under the 100 of μW....
[...]
Book•
18 Apr 2008TL;DR: This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures.
Abstract: Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.
491 citations
TL;DR: A 64-channel massive multiple-input multiple-output (MIMO) transceiver with a fully digital beamforming (DBF) architecture for fifth-generation millimeter-wave communications is presented in this paper.
Abstract: A 64-channel massive multiple-input multiple-output (MIMO) transceiver with a fully digital beamforming (DBF) architecture for fifth-generation millimeter-wave communications is presented in this paper. The DBF-based massive MIMO transceiver is operated at 28-GHz band with a 500-MHz signal bandwidth and the time division duplex mode. The antenna elements are arranged as a 2-D array, which has 16 columns (horizontal direction) and 4 rows (vertical direction) for a better beamforming resolution in the horizontal plane. To achieve half-wavelength element spacing in the horizontal direction, a new sectorial transceiver array design with a bent substrate-integrated waveguide is proposed. The measured results show that an excellent RF performance is achieved. The system performance is tested with the over-the-air technique to verify the feasibility of the proposed DBF-based massive MIMO transceiver for high data rate millimeter-wave communications. Using the beam-tracking technique and two streams of QAM-64 signals, the proposed millimeter-wave MIMO transceiver can achieve a steady 5.3-Gb/s throughput for a single user in fast mobile environments. In the multiple-user MIMO scenario, by delivering 20 noncoherent data streams to eight four-channel user terminals, it achieves a downlink peak data rate of 50.73 Gb/s with the spectral efficiency of 101.5 b/s/Hz.
302 citations
References
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Book•
21 May 2004
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Abstract: For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.
2,355 citations
"Measuring the Gap Between FPGAs and..." refers methods in this paper
...At a minimum, scan chains are typically used to facilitate these tests [ 25 ]....
[...]
22 Feb 2006
TL;DR: Experimental measurements of the differences between a 90- nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic are presented.
Abstract: This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed hoices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power onsumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.
635 citations
"Measuring the Gap Between FPGAs and..." refers background or methods in this paper
...In our past work, such settings were not used and the core-logic area gap was found to be 40 [ 11 ]....
[...]
...An early version of this paper appeared in [ 11 ]....
[...]
Book•
01 Jan 1997TL;DR: This book provides the first comprehensive introduction to Application Specific Integrated Circuits (ASICs) with a focus on semi-custom technology.
Abstract: Addressing the trend in industry away from fully custom chip design to semi-custom technology, this book provides the first comprehensive introduction to Application Specific Integrated Circuits (ASICs).
463 citations
"Measuring the Gap Between FPGAs and..." refers methods in this paper
...Similarly, CMOS standard-cell implementation is the standard approach for ASIC designs [1], [ 8 ]....
[...]
24 Feb 2002
TL;DR: The dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) is analyzed by taking advantage of both simulation and measurement, and it is concluded that dynamic power dissipation of a Virtex-II CLB is 5.9μW per MHz for typical designs, but it may vary significantly depending on the switching activity.
Abstract: This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9mW per MHz for typical designs, but it may vary significantly depending on the switching activity.
439 citations
"Measuring the Gap Between FPGAs and..." refers background in this paper
...Past studies have estimated that I/O power consumption is approximately 7%‐14% of the total dynamic power consumption [31], [ 32 ], but this can be very design dependent....
[...]
17 Aug 1999
TL;DR: Key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance are discussed, with particular focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage.
Abstract: We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. Functionality of special circuits in the presence of high leakage, SRAM cell stability, bit line delay scaling, and power consumption in clocks & interconnects, will be the primary design challenges in the future. Soft error rate control and power delivery pose additional challenges. All of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. The excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.
342 citations