scispace - formally typeset
Proceedings ArticleDOI

MEC S-box based PRESENT Lightweight Cipher for Enhanced Security and Throughput

Reads0
Chats0
TLDR
In this article, two PRESENT architectures are proposed in order to provide stronger security, with elevated performance and less power consumption, two architectures provide the option to choose one of the three MEC S-boxes, whereas the second architecture makes use of a single MECS-box to provide better security and increased performance for encryption and decryption processes.
Abstract
Cyber Physical Systems (CPS) is essential for the integration of the physical world with the virtual electronic world. The only way to provide security to these constrained environment applications is through Lightweight Cryptography. To provide stronger security, with elevated performance and less power consumption, two PRESENT architectures are proposed in this paper. The first architecture provides the option to choose one of the three MEC S-boxes, whereas the second architecture makes use of a single MEC S-box to provide better security and increased performance for encryption and decryption processes. The Standard S-box is replaced with MEC S-box, which has its own advantages, such as, less power consumption, linear time and constant space complexity. To analyse the various parameters of the proposed architectures, they are synthesized using Xilinx Virtex-7 FPGA, in Xilinx Vivado IDE. With respect to Strict Avalanche Criterion (SAC), the standard usage of S-box, nearly gives 50% SAC whereas, at least two orders of MEC S-boxes used in the proposed architectures give more than 50% SAC for the entire algorithm, thereby increasing the security of the whole process. The results depict that the proposed architecture provides a throughput of 1564.02 Mbps whereas with a lesser power consumption.

read more

References
More filters
Proceedings ArticleDOI

Security of IoT systems: design challenges and opportunities

TL;DR: A brief survey of IoT challenges and opportunities with an emphasis on security issues and several case studies that advocate the use of stable PUFs and digital PPUFs for several IoT security protocols are presented.
Proceedings ArticleDOI

Lightweight Cryptography for FPGAs

TL;DR: This paper introduces block cipher independent optimization techniques for Xilinx Spartan3 FPGAs and applies them to the lightweight cryptographic algorithms HIGHT and Present, which are the first reported of these block ciphers on FPGA.
Proceedings ArticleDOI

Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher

TL;DR: A novel FPGA-based design for the lightweight block cipher PRESENT and its implementation results are presented, which allows to study area-performance trade-offs and thus constructing smaller or faster implementations.
Proceedings ArticleDOI

RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT

TL;DR: Two different FPGA implementations of the lightweight cipher PRESENT are proposed, which occupy only 83 and 85 slices and produce a throughput of 6.03 and 5.13 Kbps at 100 KHz system clock on a Xilinx Spartan XC3S50 device.
Proceedings ArticleDOI

Design space exploration of present implementations for FPGAS

TL;DR: The results highlight that PRESENT is well suited for high-speed and high-throughput applications, especially its hardware efficiency, i.e. the throughput per slice, is noteworthy.
Related Papers (5)