Journal ArticleDOI
Method to Simulate Rise Time of Current Drawn by a Microprocessor
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TLDR
In this article, several exponential functions with varying time constants are staggered and combined at different starting time values to generate the effective current profile, which was used for noise estimation, using a realistic jitter-based distribution function compared to a step function used in existing models for the initial small amount of saturated current ramp.Abstract:
We have developed a new method to simulate the effective rise time of current drawn by each cell in a microprocessor so that the total noise is consistent with values measured at the power and ground reference points inside the die. Normally, the measured values are much smaller than simulated values. In this paper, several exponential functions with varying time constants are staggered and combined at different starting time values to generate the effective current profile which was used for noise estimation. The model utilizes a realistic jitter-based distribution function compared to a step function used in existing models for the initial small amount of saturated current ramp. The practical model developed in this paper is useful for optimizing the cost and performance of microprocessors.read more
Citations
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Journal ArticleDOI
Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback
TL;DR: In this article, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation.
Proceedings ArticleDOI
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip
TL;DR: Gating logic is incorporated to offer solution to PSN occurrence in CMOS circuits by controlling di/dt, which is generated by the linear current ramp of present day high performance CPU.
Journal ArticleDOI
Innovative Scaling Method to Minimize Cost of Integrated Circuit Packages and Devices
TL;DR: In this article, an analytical technique to scale the power delivery solutions for a given integrated circuit (IC) chip that can draw currents to cause enough inductive noise for the IC to fail is presented.
Journal ArticleDOI
Variation aware intuitive clock gating to mitigate on-chip power supply noise
TL;DR: In this paper, a new clock gating scheme incorporating leakage control transistor, which simultaneously curbs the static and dynamic power along with the alleviation of power supply noise (PSN) in silicon chips by smartly controlling the current ramp (di/dt) and average current i(t): the main contributors to PSN.
Journal ArticleDOI
Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range
TL;DR: An ultra-low power design of single ended hybrid Current Starved-CMOS (CS- CMOS) Ring VCO with wide tuning capability is tendered to prove the robustness and scalability of the proposed circuit.
References
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Proceedings ArticleDOI
Integrated power supply frequency domain impedance meter (IFDIM)
A. Waizman,M. Livshitz,M. Sotman +2 more
TL;DR: In this article, an integrated and self-checking on-die current throttling method that accurately measures CPU's power delivery impedance profile from the die up to the voltage regulator is presented.
Proceedings ArticleDOI
CPU power supply impedance profile measurement using FFT and clock gating
TL;DR: In this paper, a CPU bypass mode clock gating and oscilloscope FFT features enable accurate measurement of a CPU's power delivery network impedance profile up to 100MHz, using self-checking.
Proceedings Article
A semi-empirical approach to determine the effective minimum current pulse width (T) for an operating silicon chip
TL;DR: In this article, a semi-empirical approach is proposed to determine the effective minimum time interval (T) over which voltage noise affects the performance of a silicon integrated circuit, which corresponds to simultaneous voltage collapse of the power delivery network, and current demand from the silicon.
Proceedings ArticleDOI
Measurement-to-modeling correlation of the power delivery network impedance of a microprocessor system
TL;DR: An automated system for measuring the power delivery impedance profile on a functional system is presented in this paper, where the data collected by this system is used to assess the accuracy of a distributed power delivery system model.
Proceedings ArticleDOI
A method to measure impedance of chip/package/board power supply system using pseudo-impulse current
TL;DR: In this article, a method to measure the impedance Z(f) of a chip/package/board power supply system using pseudo-impulse current is described, which can be easily applied to the digital systems with synchronous clocking systems.