Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks
24 Jun 2013-pp 156-163
TL;DR: This paper proposes a methodology allowing effective placement of variable-size IPs on reconfigurable regions which are sized to the smallest IP of a given application, and shows a gain in hardware utilization resources up to 40% for given hardware tasks and the lesser context changing time which is driven by the size of the reconfigured region used to task implementation.
Abstract: Dynamic partial reconfiguration (DPR) of FPGA-based architectures offers a high degree of flexibility and is often an appropriate solution for applications needing dynamically changing contexts. The standard design flow used for design of these architectures still suffer from a lack of adaptability when confronted with applications to implement consisting of variable-size hardware tasks or IP (Intellectual Property) cores. Thus induced heterogeneity may cause wrong placement of hardware tasks (IPs) on a chip leading to a sub-optimal use of available hardware resources and therefore a decrease in the system performances. This paper addresses the problems of effective design of reconfigurable regions on the FPGA device with regard to needed hardware resources for a given application. We propose a methodology allowing effective placement of variable-size IPs on reconfigurable regions which are sized to the smallest IP of a given application. Its validation and benefits are shown on the example of video transcoding from MPEG2 to H.264 video stream, especially in the case of reconfigurable region partitioning used to implement hardware tasks for the entropy encoding (CAVLC / VLC). The obtained results show a gain in hardware utilization resources up to 40% for given hardware tasks and the lesser context changing time (up to 2 times faster) which is driven by the size of the reconfigurable region used to task implementation.
Citations
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Journal Article•
TL;DR: In this paper, the authors present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex FPGA's reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks.
Abstract: We present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex To that end, the FPGA's reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks A bus-based communication infrastructure allows for task communication and I/O We discuss the design of the runtime system and its prototype implementation on an reconfigurable board architecture that was specifically tailored to reconfigurable hardware operating system research
69 citations
Patent•
11 Nov 2014TL;DR: In this paper, a circuit design is created in a computer memory in response to user input to a computer processor, and a virtual socket (312) is instantiated in the circuit design, and one or more reconfigurable modules (402, 404, 406) are instantiated (206) in the virtual socket in response for user input.
Abstract: A circuit design is created (202) in a computer memory in response to user input to a computer processor. The circuit design has a static portion (102). A virtual socket (312) is instantiated (204) in the circuit design in response to user input, and one or more reconfigurable modules (402, 404, 406) are instantiated (206) in the virtual socket in response to user input. The static portion of the circuit design is coupled (210) to the one or more reconfigurable modules, and configuration data are generated (212) from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.
6 citations
14 Jul 2014
TL;DR: This work considers optimization techniques for a problem that requires a valid scheduling and allocation of tasks on Field Programmable Gate Arrays (FPGAs), and presents an Integer Program that partitions the tasks in such a way that all constraints can be met and the reconfiguration overhead is minimized.
Abstract: We consider optimization techniques for a problem that requires a valid scheduling and allocation of tasks on Field Programmable Gate Arrays (FPGAs). A concrete application on a scientific space instrument arises in the context of ESA's Solar Orbiter mission; making use of dynamic reconfiguration allows a good and flexible use of resources, but the resulting packing and scheduling problems in the presence of inhomogeneous allocation resources are quite challenging. In our scenario, modules are described by three parameters: their resource demands for different types of resources, their priority, and their clock frequency. These are to be allocated on an FPGA that provides a number of different resources that are available at specific locations. We first present an Integer Program that partitions the tasks in such a way that all constraints can be met and the reconfiguration overhead is minimized, and then give methods for allocating the processing modules of the partitioned tasks on the FPGA. We evaluate our methods on a real application of the Solar Orbiter PHI instrument. The results obtained indicate computational efficiency and a remarkable solution quality.
4 citations
Cites background from "Methodology and reconfigurable arch..."
...For slightly more general problems in the context of reconfigurable computing (which are still simpler than MAP), consider [2], [7], [12], [19]–[21], [26], and [1] for a relatively recent survey of optimization methods in reconfigurable computing....
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Dissertation•
02 Dec 2013
TL;DR: Cette these s'inscrit dans ce contexte et propose une methodologie de modelisation SystemC d'architectures reconfigurables dynamiquement dans le cadre du projet ARDMAHN finance par l'Agence Nationale de the Recherche.
Abstract: Malgre des avantages certains en terme d'adaptabilite et en gain de surface, la reconfiguration dynamique sur FPGA a du mal a etre utilisee dans l'industrie. Le manque de moyens et de methodes d'evaluation d'une telle architecture en est la cause majeure. Pire, aucun outil officiel ne permet aux developpeurs de determiner facilement un ordonnancement de la reconfiguration adapte pour une architecture donnee.
Cette these s'inscrit dans ce contexte et propose une methodologie de modelisation SystemC d'architectures reconfigurables dynamiquement. Cet outil d'aide a la conception permet de faire gagner un temps considerable lors de la phase de conception en fournissant une premiere estimation des performances et des ressources necessaires au developpement de l'architecture. Il permet egalement le developpement et la validation de scenarios d'ordonnancement de la reconfiguration, tout en respectant les contraintes temps reel liees a l'application.
Afin de valider notre modele sur une application reelle, des IP de transcodage video ont ete developpees et seront detaillees. Cette application consiste en la realisation d'un transcodeur H.264/MPEG-2, rendu auto-adaptable grâce a l'utilisation de la reconfiguration dynamique. Ces travaux ont ete menes dans le cadre du projet ARDMAHN finance par l'Agence Nationale de la Recherche portant la reference ANR-09-SEGI-001
1 citations
References
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TL;DR: To help investigate the viability of connected FPGA systems, the authors designed their own architecture called Garp and experimented with running applications on it, investigating whether Garp's design enables automatic, fast, effective compilation across a broad range of applications.
Abstract: Various projects and products have been built using off-the-shelf field-programmable gate arrays (FPGAs) as computation accelerators for specific tasks. Such systems typically connect one or more FPGAs to the host computer via an I/O bus. Some have shown remarkable speedups, albeit limited to specific application domains. Many factors limit the general usefulness of such systems. Long reconfiguration times prevent the acceleration of applications that spread their time over many different tasks. Low-bandwidth paths for data transfer limit the usefulness of such systems to tasks that have a high computation-to-memory-bandwidth ratio. In addition, standard FPGA tools require hardware design expertise which is beyond the knowledge of most programmers. To help investigate the viability of connected FPGA systems, the authors designed their own architecture called Garp and experimented with running applications on it. They are also investigating whether Garp's design enables automatic, fast, effective compilation across a broad range of applications. They present their results in this article.
478 citations
"Methodology and reconfigurable arch..." refers background in this paper
...This issue has been widely studied for the temporal placement of hardware IPs [9], [10]....
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...Hence, the hardware IPs (PR modules) implemented on a same reconfigurable region must have a common wrapper....
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...These wrappers are defined by the inputs and outputs ports of hardware IPs to implement....
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...Existing methods have shown their effectiveness in the case of simple data flow graphs (DFG), but remain ineffective and almost impossible to implement complex hardware IPs....
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...An aggregation technique guaranteed in this case is the possibility of implementing hardware IPs larger than the elementary partition....
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01 Aug 2006
TL;DR: In this article, the authors describe architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs, augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules.
Abstract: The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinx's commercial CAD tools
308 citations
"Methodology and reconfigurable arch..." refers methods in this paper
...The alternative to this solution is the use of pre-routed macros also called bus macros [14]....
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01 Jan 1999
TL;DR: The JBitsTM software is a set of JavaTM classes which provide an Application Programming Interface (API) to access the Xilinx FPGA bitstream, which permits all configurable resources like Look-up tables, routing and the flip-flops in the FPN to be individually configured under software control.
Abstract: The JBitsTM software is a set of JavaTM classes which provide an Application Programming Interface (API) to access the Xilinx FPGA bitstream The interface operates on either bitstreams generated by Xilinx design tools, or on bitstreams read back from actual hardware This permits all configurable resources like Look-up tables, routing and the flip-flops in the FPGA to be individually configured under software control
269 citations
"Methodology and reconfigurable arch..." refers methods in this paper
...The addition of these elements to the final design is obtained by design bitstream manipulation using Jbits [4]....
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20 Jun 2011
TL;DR: This paper will provide documentation on the Xilinx Design Language and reveal several use cases for this language, which can be used to constrain systems or to directly implement modules or macros forXilinx FPGAs.
Abstract: With the Xilinx Design Language (XDL), the FPGA vendor Xilinx offers a very powerful interface that provides access to virtually all features of their devices. This includes on one side the generation of complete device descriptions containing information about the FPGA primitives and the routing fabric. On the other side, XDL can be used to constrain systems or to directly implement modules or macros for Xilinx FPGAs. In this paper, we will provide documentation on the language and reveal several use cases for this language.
81 citations
"Methodology and reconfigurable arch..." refers methods in this paper
...Step 4: Modification of Pin Partition routing: An XDL file is generated from the NCD file of the latest PR module design....
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...This is done by editing the netlist of blank configuration using Xilinx Design Language (XDL) [15] and extracting the routing information of Pin Partitions....
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...The main contribution of this paper is to bring to the designer an easy-to-use method to adapt PR regions to variable-size PR modules based on the use of Xilinx PR design flow and Xilinx Design Language (XDL)....
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Journal Article•
TL;DR: In this paper, the authors present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex FPGA's reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks.
Abstract: We present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex To that end, the FPGA's reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks A bus-based communication infrastructure allows for task communication and I/O We discuss the design of the runtime system and its prototype implementation on an reconfigurable board architecture that was specifically tailored to reconfigurable hardware operating system research
69 citations