Toward Effective Utilization of Timing Exceptions in Design Optimization
Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang
University
of
California. San Diego
+--
"-----~---~---~---~----+
0.9
Fig. I. Normalized runtime, area and TNS for the AES cipher testcase after
placement and routing, versus the number of timing exceptions applied.
lin
Sp
yGlass[17]
, timing exceptions are generated from a list of timing
critical paths reported from
STA
tools, and each critical path is then tested
whethertrue or false. Hence, auto-generated exceptions from
commerci
al tools
resemble the timingreports format whichdefines one startpoint, one endpoint,
and several intermediate points along a timing path. However, designers
define timing exceptions based on the
knowledge
of functionality, and use
simplest forms, omitting detailed points in timing paths, to reduee the effort
of describing many timing exceptions
manuall
y.
1.05
1.1
0.95
281931409670482819
Number of
timin
g exceptions
-.
Normalized TNS
..... . Normalized area
-+-
Nonnalized runtime
35
30
"
25
·E
c
20
E
""
15
"
.
~
..
10
E
..
0
z
of lines in the 'golden' constraint file at signoff. Hence, manual
identification and specification
of
valid timin g exceptions is often
infeas ible. Recent commercial tools such as
Cobalt [20], FishTail [21]
and
SpyGlass [17] exemplify the drive for more effective automatic
gene ration and verification
of
timing exceptions with minimum
designer effort .
It is expected that such tools will be very helpful
in improving designer productivity.
I
Ideally, adding timing exceptions on the critical path
of
a design
will reduce constraints and optimization effort, so that runtime and
area will also be reduced. However, adding more exceptions does
not always result in better QOR and TAT, since too many exceptions
requiring special care in design optimization can give rise to negative
side effects on optimization runtim e and quality. Figure I shows the
rapid runtime increase with increasing number
of
timing exceptions -
without improving des ign area , and with small improvement in total
negative slack (TNS). The test case is the
AES cipher circuit in Table
v.
Given the above, it is necessary to analyze the benefits
of
intro-
ducing timing exceptions in design optim ization processes, and to
develop a new design methodology that effectively utilizes timing
exceptions. In this paper, we explore the impact
of
timing exceptions
in the design implementation flow through experiments that address
three fundamental driving questions:
I) Do timing exceptions help or hurt in design optimization?
2) Which exceptions give net benefit when applied?
3) When can such help ful exceptions be identified with sufficient
accuracy?
Our contributions are summarized as follows.
• We evaluate the impacts
of
timing exceptions on design QOR
and TAT, and show that not all timing exceptions are beneficial
in design optimization processes.
• We analyze the characteristics of timing exceptions and classify
effective vs. ineffective timing exceptions.
• We exam ine various potential metrics to quantify the effective-
ness
of
timing exceptions.
Abstra
ct-
Timing exceptions in
Ie
implementation processes, es-
pecially timing verification, help reduce pessimism that arises from
unnecessary timing constraints by masking non-functional critical paths.
Ideally, timing exceptions should always be helpful for quality of results
(QOR) metrics such as area or number of timing violations, and for
design turnaround time
(TAT)
metrics such as tool runtime and number
of design iterations. We expect this positive impact since timing exceptions
reduce the number of constraints that the design optimization must
satisfy.
In this work, we evaluate the impact of timing exceptions on design
QOR and
TAT,
with respect to (1) the forms in which timing exception
are declared, (2) the timing criticality of the target paths, (3) the number
of applicable exceptions, and
(4) the design stages at which timing
exceptions are extracted and applied. From our experimental analyses,
we observe that applying more exceptions in commercial tool flows does
not consistently lead to better QOR, and often only increases runt ime
unnecessarily. We analyze potential causes of unwanted impacts of timing
exceptions, and examine various methods to filter out ineffective timing
exceptions.
Implications of our study give preliminary guidelines for designers
and
EDA vendors regarding the use of timing exceptions in design
optimization processes.
Our
work hopefully lays a foundation for novel
design methodologies that can maximize the benefits of timing exceptions.
I. I
NTROD
UCTION
As the complexity and size of
Ie
designs increase , exhaustive
funct ional verification using event-based
dynamic logic simulations
has reached its limits. Gene ration
of
vectors considering all feasible
operating scenarios is difficult, and requires excessive simulation
runtime for large designs. As a result, the
static timing analysis
(STA) verification methodology has become ubiquitous for design
signoff. STA cons iders all poss ible signal trans itions in a design,
but in a static way. Since STA doe s not fully consider whether a
given signal transition can occur in actual operation
of
the design,
the STA verification methodology can report timing failures on
timing paths that are not exercised during actual operations . Thus ,
timing optim ization bas ed on (incremental) STA results will expend
unnecessary effort to meet timing requirements for non- funct ional
paths.
To avoid such unnecessary pessimism in STA,
timing exceptions
are used in the desig n verification stage to filter out violations that
correspond to non-functional timing paths. There are two major
types
of
timing exceptions:
(I)
fal
se paths that cannot be sens itized
by any input vectors , and (2)
multicycle paths along which signal
propagation does not have to complete within one clock cycle.
The former completely ignores timing requirements, while the latter
relaxes timing requirements for the specified paths .
False paths in logic circuits have been studied in previous works
[1], [2], [3] and [4]. Multicycle paths have also been investigated in
the literature [5], [6], [7]. Liou et al. [8] present a false-path-aware
statistical timing analysis framework. Higuch i et al. [9] investigate
on a multicycle path analys is and detecting method. Yang et al. [10]
propose an algorithm to identify multicycle and false paths . However,
most
of
the prev ious works present methods to identi fy false paths or
multicycle paths, and focus on the use
of
timing exceptions at timing
analysis and verification stages .
Separately from academic investigations, designers have long
analyzed timing paths and specified timing exceptions manually.
Such manual works are time-consuming and always error-prone.
Furthermore, with the increase of system-on-chip (SOC) design size
and complexity, timing exceptions can easily take up many thousands
978-1-4244-6455-5/10/$26.00
czorc IEEE
54 11th Int'l Symposium on Quality Electronic Design
• We give guidelines and a design methodology to utilize timing
exceptions in design optimization.
The remainder
of
our paper is organized as follows . Section II
presents motivational hypotheses on the insertion
of
timing excep-
tions in design optimization processes. The hypotheses are analyzed
experimentally in Sections III, IV and V. Based on observations from
our experiments, in Section VI we propose useful tips and a potential
design methodology to use timing exceptions more effectively in de-
sign optimization. Finally, Section VII summarizes our conclusions.
false path
mult icycle
path
Fig. 2. Categorization of timing exceptions.
II.
BACKGRO
UND AND
DRIVI
NG
QU
ESTIO
NS
Timing exceptions are described in Synopsys Design Constraints
(SOC) format which defines detailed timing requirements for the
design, e.g., clock cycle time and waveforms, I/O delays , and timing
exceptions. The information can be passed to synthesis, timing-driven
placement and routing tools, and final signoff static timing analysis
(STA).
Synopsys also provides a guideline [12] for using the SOC
format.
Designers usually describe timing exceptions considering func-
tional or architectural attributes of the design . Automatically gen-
erated timing exceptions can be added from commercial tools, such
as those noted above, which support a path-validation function .
In the SOC, timing exceptions for false paths and multicy-
c1e paths are defined using the keywords
'set.false.path ' and
'set.multicycle.path ', respectively. Timing exception definitions can
be categorized as shown in Figure
2.
false Path [ -f
rom
clock
-to
. input/ output
[
multi-
Cycle Path -through
[.
-f
rom
-to register
-f
rom
-through-to
Class
[
userde
fin
ed
automatically
generated
Type Form Point
SDC File
set false
p ath -from REG_A.Q -throu gh U2.Y -through U3.Y -10 REG
_C
D
set false
p ath -from REG_I3.Q -to REG_D .D
set_muh icycley ath -set up 2 -fro m REG_B.Q -to REG_D .D
Fig. 3. Descriptions of exceptions
according
to the
format.
designers must be concerned with. And, false or multicycle paths
reduce the number
of
negative-slack paths, so that timing closure
is more easily achieved. In addition, reduced constraints prevent
excessive optimization such as upsizing of cells on non-functional
timing paths; this leads to reduction
of
design area.
On the other hand , added exceptions hurt because they add com-
plexity in optimization and extra care-abouts in timing analysis and
optimization processes. Moreover, from our experiments it appears
that the EDA industry, by convention, preserves exceptions on nodes
in a circuit throughout the optimization process. This preservation
of
exceptions on nodes prevents restructuring and reduces the design
solution space: feasible solutions with restructuring are excluded from
consideration.
Intuitively, there must be a tradeoff between setting timing excep-
tions and discarding timing exceptions. In Section III, we examine
the impact
of
timing exceptions on the design optimization process
in detail.
Non-critical e
xceptio
ns
with 'through' point
Non-critical exceptions
w/o 'through' point
Effec tive exce ptions
Timing Slack 0
Critical exceptions
w/o 'through' points
2)
Which
exceptions give net benefit
when
inserted?
Timing
exceptions can be classified not only by their format but also by the
timing criticality
of
the associated paths. Timing criticality implies
negative timing slack on paths specified by the exceptions before the
timing exceptions are applied. Hence, the 'exception space ' has two
dimensions as shown in Figure 4. Within this exception space, we
examine which exceptions are effect ive versus ineffective for timing
optimization. In Section IV, we seek to identify beneficial exceptions
in this exception space.
In the description
of
exceptions, paths are lists
of
"<from",
"<through" and
"<to
" points. Each point can be a clock or input/output
port, or a pin
of
a cell instance including registers (flip-flops) and any
combinational cells.
2
Figure 3 shows an example
of
timing exceptions in SOC. In
this example , we declare three forms
of
exception - false paths
with
"<through" points , false paths without "<through" points, and
multicycle paths between two registers . Multicycle paths are usually
defined between two registers , between input/output points , or be-
tween different clock domains. In general,
"<through" points are not
used with multicycle path definitions.
Timing exceptions between different clock domains and false paths
using only start
(-from) or end (-to) points are usually specified
by users; these are often called user-defined false paths. Timing
exceptions between registers or input/output ports can be additionally
extracted and applied using commercial CAD tools. In this work,
we focus on whether the generated timing exception is beneficial.
We perform experiments on the timing exceptions which are defined
between two registers or between a register and an input/output pin.
Our work is motivated by three driving questions.
1) Do
timing
exceptions help
or
hurt?
On the one hand, added
exceptions help because constraints are removed from optimization.
That is, exceptions reduce the number
of
timing problems that Fig. 4. Exceptions space
according
to the
format
and criticality.
2A port of hierarchical
modules
can also be a point for timing exception
declaration.
Howev
er,
placement
and routing tools are in
general
based on
the
assumption
of
flatten
ed designs, so that hierarchical
module
ports can
disappear during pl
acement
and routing. Therefore, it is preferred to use
physically m
eaningful
points, such as input/output pins of cells or
primary
input/output ports, to specify timing exceptions.
3)
When
should
exceptions be identified
and
applied?
There are
several stages in the implementation flow - synthesis, placement,
clock tree synthesis (CTS), and routing stages. Between stages,
or within each stage, timing optimization can be executed several
Fig. 5. Experiment
design
for
extraction
stageand
application
stageof
timing
exceptions
.
times. Our initial intuition regarding this question is that (i) higher
benefit can be obtained when timing exceptions are extracted as late
as possible, since more accurate timing information is available in
later design stages with the convergence
of
spatial embedding and
parasitics ; on the other hand, (ii) higher benefit can be obtained
when timing exceptions are applied as early as possible, since we
can maxim ize the benefit
of
timing exceptions as much as possible
before performing excessive timing optimizations.
Figure
5 illustrates feasible scenarios to extract and apply excep-
tions. DC, PLACE , PLACE
-OPT,
CTS
,
CTS
-OPT,
and
ROUTE
respectively denote synthesis (using Synopsys Design Compiler),
placement, timing optimization after placement, clock tree synthesis,
timing optimization after clock tree synthesis, and routing. Exceptions
extracted after the DC stage can be applied before the PLACE,
PLACE-OPT, CTS and CTS-OPT stages. Exceptions extracted after
the PLACE-OPT stage can be applied in advance to the following
stages. However, if we apply exceptions at a stage which is far
from the stage at which the exceptions were extracted, most
of
the
exceptions with "through" points would not be feasible since the
name or structure
of
a given point (in the exception specification)
can be changed during optimization. In Section V, we experimen-
tally determine when exceptions should be extracted and applied
to achieve the best QOR results. Our experiments extract timing
exceptions from each stage - after placement (PLACE), placement
optimization (PLACE-OP7), CTS, CTS optimization (CTS-OP7) and
routing (ROUTE) - and apply the exceptions to the next stage so
as to identify the most beneficial design stages for extraction and
application
of
exceptions.
C
out
s
A -
---+------\\
B
AND2
Fig. 7.
Full-adder
circuitin
RCA
.
TABL
E I
WORST
NEG ATIV E SLACK (ns) AND ARE A (um
2
) OF
4-8IT
RIPP
LE
CARRY
ADD ER . FP AN D MCP D
ENOTE
FALS E PATH AN D MULTICY CL E PATH,
RESP E
CTIV
ELY.
on these paths in different ways:
(I)
false paths (FP) with "through"
points, (2) false paths without "through" points, (3) multicycle paths
(MCP) with "through " points, and (4) multicycle paths without
"through" points.
Applying these different types
of
exceptions, we analyze quality
of
optimization in three different commercial tools, i.e., Synopsys
DesignCompiler (DC) [14], Cadence SOC Encounter (SOCE)
[18],
and Synopsys Astro (ASTRO) [16]. Table I shows the timing and area
results from each tool. For DC, we measure timing and area after
performing incremental timing optimization. For SOCE and ASTRO,
we measure timing and area after perform ing placement and routing
with timing optimizations.
Without FP wi FP wlo MCP wi MCP wlo
exceptions
'through' 'through' ' through' 'through'
DC
WNS -0.040 -0.540
0.000
-0.540
0.000
Area 244.8 166.3 196.9 166.3 196.9
SOCE WNS -0.059 -0.337 -0.035 -0.337 -0.035
Area
226.4
201.6 233.3
201.6
233.3
Astro WNS
-0.253 -0.290
-0.136 -0.290
-0.136
Area 212.4 192.6 209.2 192.6 209.2
ROUTECTS-OPTCTS
Non-feasible for exceptions
..............
with "through" points
<,
PLACE PLACE-OPT
DC
III.
IMPA
CT
OF
TIMING
EXCEPTIONS
IN
OPTIMIZATION
The first driving question above elicits the hypothesis that added
timing exceptions help remove overconstraints, but can increase
optimization complexity. To prove this hypothesis, we perform exper-
iments with the two types (false and multicycle paths)
of
exceptions.
In addition, we study the impact
of
"through" points, which may
prevent circuit restructuring and degrade timing results.
We also compare two different forms
of
timing exceptions
compact and equivalent complex form. Figure 8 shows three compact
forms and their equivalent forms
of
exceptions (upper) with complex
forms
of
equivalent exceptions (lower). We use AES cipher circuit
(Table V) as a testcase. We take 20 start ("-from") points from k-top
critical paths, and we make equivalent complex form exceptions by
specifying all corresponding end ("-to") points. We define compact
and complex form exceptions for "-to" and "<through" cases in the
same way.
A. Difference
of
Timing Exceptions
We compare the impact
of
different types
of
timing exceptions.
We use a 4-bit ripple carry adder (RCA) as shown in Figure 6 to
analyze the impact
of
timing exception types. A full adder circuit is
shown in Figure 7.
-
Full adder-O
f-
Full adder- I
I-
Full adder-2
I-
Full adder-3
I-
c,
A[O] 8[0]
A[I ] 8[ t ] A[2 ] 8[2] A[3] 8[3]
-from
.
----
--
-
-----
-
--
S
-to
-from .,. I I
. :;:::::
:::--.
12
S •••••
··
····
. I
j
(a)
-to
-
----
------
---
-.
I
-from
s,
•....
...... -to
S2
.·.::
:
~.
~::).I
S j .
(b)
-through
--
-------.--------
m
-from -to
s, • ...
-throu
gh
...•
I,
S2
~-<
~::
)~
r
::
~~::
'-~
12
s, • ... ·
'.I
j
(c)
S[O]
S[I ] S[2] S[3]
Fig. 8. Three
compact
forms
andtheir
equivalent
forms
in
timing
exceptions
.
Fig. 6. 4-bit
ripple
carry adder.
We choose three timing paths arbitrarily, i.e., from A
[O
] to
Caul
,
from B
[O
] to
Caul,
and from C
in
to
Caul,
and define timing exceptions
Table II shows optimization results after applying exceptions. In
the results, compact forms
of
timing exceptions show better timing
and TAT results than complex forms. And, TNS is degraded with
"through" point in case (c).
TABL
E II
T IMING
SLA
CK AND AR EA RESULTS AFT ER APPLYING COMP ACT AN D
EQUIVALENT COMPLEX FORM OF TIMING EXCE PTIONS.
false paths. Thus, we design a scalable artificial circuit as shown in
Figure 10.
Fig. 9. Full-adder circuit after optimization with "through" points in (A) and
without "through" points in (B).
It is difficult to analyze the impact of timing exceptions in large real
designs due to the complexity and uncontrollability
of
the number of
STAGE - 2
.3
. 4 ...STAGE - I
UNIT circuit
# of all paths 20 100 2,500 1,562,500
# of false paths 2 20 916
941,636
clock period (ns)
0.4 0.8 1.6 3.2
TA B
LE
III
T il E NUMBER OF PATH S AND TARGET FREQU ENCY IN THE ARTIFIC IAL
CIRCUIT.
We perform placement and routing (P&R) for five cases, i.e.,
without false paths, with 25%
of
all false paths, with 50%
of
all
false paths, with all false paths, and with multicycle path (MCP)
exceptions only. 25% and 50% false paths are selected according
to the ascending order
of
timing slack values, i.e., top 25% and
50%
of
critical paths are selected. For P&R, we use a traditional
timing-driven implementation flow with Cadence SOC Encounter,
and a signoff timing analysis flow with Synopsys PrimeTime
vB-
2008.12-SP2 [15]. In the artificial circuits, real multicycle paths do
not exist. So, we define four multicycle paths arbitrarily, i.e., from
I
N...2
and IN.3 to O
UT...2
and OUT.3 among 16 register-to-register
paths. After placement and routing (P&R), we measure worst negative
slack (WNS), total negative slack (TNS), area, and runtime (TAT).
Table IV summarizes timing, area, and runtime with respect to the
number of timing exceptions applied.
The circuit consists
of
cascaded unit circuits, with the unit circuit
having one select port and four input-output pairs. The unit circuit
contains two false paths, so that we can control the number
of
false
paths easily by cascading the unit circuit.
To calculate the total number
of
paths, we count all incoming paths
at the four output nodes
of
each stage. Initially, for l-stagc circuit,
the numbers
of
incoming paths for output nodes are N I,OU T.3 = 5,
N \ ,OUT..2 = 5, N \ ,OUT. I = 5, and N \ ,OUT. O= 5, respectively. Summing
up the number
of
incoming paths
of
each output node gives total
number
of
paths in the l-stage circuit. The number
of
paths in n-
stage circuits can be calculated recursively as:
Fig. 10. Artificial circuit which is scalable by cascading a unit circuit.
I stage
-I
I stage
-2
I stage--4 I stage- S
. _ '
N n,
IO
lal =
8N
n
_ 1,OUT_3 +4 N
n
_ 1
,o
UT ..2 +4 N
n
_ 1
,o
UT _I +4N
n
- 1
,o
UT_O
where the number
of
incoming paths at the output nodes
of
n - 1
(
Nn-I
,OUT .3 ,.. .N
n
- I,OU
LO
) is also calculated recursively. The coeffi-
cients, i.e., 8 and 4, in the equation indicate the number
of
branches
from the output nodes
of
n - l-stage circuit.
The number
of
true paths in the circuit is then calculated using the
same method after removing false paths in the circuit, and finally,
the number
of
false paths is calculated by subtracting the number
of
true paths from the total number of paths.
We apply different clock periods for each circuit, since the length
of
combinational paths is different and proportional to the number
of
stages. Table
II1
summarizes the number
of
all paths and false paths
in each artificial circuit with different stages.
AND2
(B)
AN D2
(A)
Form # FP
Bef
ore optimization Afte r optimization
WNS TNS WNS TNS Runtime
wlo FP
0
-00401 -71.966 -0.242 -53.359
0:16:\4
(a)
comp
act
20
-0.356 -69.268 -0.234 -49.911 0:18:38
(a) complex 390 -0.356 -69 .268 -0.235
-53.145
0:24:45
(b) comp act 20
-0.3\9
-65
.0\9
-0.238 -48.905 0:15:06
(b) complex 818 -0.319
-65.019 -0.236
-53
.\9\
0:24:0 7
(c)
compact
20
-0.383 -70.86\ -0.25 7
-54.357
0:14:32
(c) complex 476
-0.383 -70.861 -0.240
-55.111 0:19:2 7
From the experimental results, we observe the following.
1) Comparison
of
the results between "Without exceptions" and
"FP wlo through" or "MCP wlo through": timing is improved
and area is reduced. This is because three critical paths are
removed due to timing exceptions.
2) Comparison
of
the results between FP and MCP: FP and
MCP have the same impacts on timing and area for all three
optimization tools, DC, SOCE and
ASTRa.
3) Comparison
of
the results between "wi through" and "w/o
through": we observe that, in both FP and MCP cases,
"wi through" cases show significant degradation
of
timing,
compared to "w/o through" cases.
4) Comparison
of
the results between compact form and equiv-
alent complex form, we observe that compact form is more
beneficial than complex form considering timing slack and
runtime.
The first and second observations are intuitive. However, the
third and fourth observations need further analysis. In the following
subsection, we analyze the third observation in detail.
B. Experiments on 'through ' Points
From Table 1, we also observe that the area from "wi through" is
significantly smaller than that from "w/o through". We can conclude
that "through" points prevent aggressive optimization. The reason
for timing degradation and smaller area due to "through ' points may
stem from the fact that optimization tools
try to preserve the points
given by timing exceptions. Hence, aggressive timing optimizations
while sacrificing area, such as logic restructuring, are prevented for
the points specified by timing exceptions. Figure 9 compares the
resulting circuits after optimization with "through" points in (A)
and without "through" points in (B). During optimizations without
"through" points, cells in a critical path (from
Cin to COUI) have
been changed from
AND2 - OR3 to A0121 - IN V. However, with
"through" points, original circuit topology is maintained.
TABLE
IV
QOR RESULTS AFTER P&R WITH
SOC
ENCOUNTER. FP DENOTES FALSE
PATHTIMING EXCEPTIONS ARE APPLIED .
I SOCE I QOR I 0% FP I 25% FP I 50% FP I 100% FP I MCP
WNS (ns) -0.314 -0.311 -0.311 -0.305 -0.262
stage-I TNS (ns) -1.100 -1.1I 1 -1.I1I -1.094 -0.948
Area 254.7 268.1 268.1 252.6 280.8
WNS (ns) -0.233 -0.226 -0.189 -0.219 -0.182
stage-2 TNS (ns) -0.786 -0.838 -0.721 -0.761 -0.676
Area 352.8 293.5 31I.2 288.6 320.3
WNS (ns) -0.042
-0.138 -0.132 -0.094
0.000
stage-4 TNS (ns) -0.089
-0.449
-0.466 -0.288
0.000
Area
460.8
360.6 370.4 378.9 452.3
WNS (ns)
0.002 -0.459 -0.325
-0.310
0.000
stage-S TNS (ns)
0.000
-1.729 -1.241 -1.185
0.000
Area 581.4 503.1 505.9
512.3 601.9
TAT 0:03:37 0:24:38 1:09:25 6:53:33 0:02:51
optimization stage
of
Synopsys DesignCompiler (DC) Y-2006.06-
SP5 [14] We use multicycle paths without "through" points and false
paths with "through" points. Figure 12 shows experimental results
when we apply top-I 0%, 25%, 50% and 100%
of
exceptions in
descending order
of
criticality (timing slack). Figure 12 shows the
worst negative slack after the incremental optimization with different
number
of
timing exceptions. From the figure, we observe that WNS
is not improved by non-critical exceptions, and in fact remains the
same as when no exceptions are applied (0% cases in Figure 12).
However, critical false paths and multicycle paths improve timing
slack. Critical timing exceptions without "through" points (Critical
MCP) effectively reduce the worst timing slack, but critical timing
exceptions with "through" points (Critical FP) do not significantly
improve timing slack.
Fig. 12. Timing results (WNS) after applying critical and non-critical
exceptions.
B_ Effective Timing Exceptions
We can use critical exceptions rather than non-critical excep-
tions. However, not all critical exceptions are beneficial: the critical
exceptions can be either effective or ineffective for design timing
optimization. Ineffective exceptions need to be avoided in design
optimization.
Effective timing exceptions. To be beneficial in design optimization,
timing exceptions need to
(I)
tum negative slack to positive, (2)
improve large negative slack to the point where it can be turned
to positive with a simple sizing optimization, or (3) improve timing
slack
of
non-critical paths which may have either positive or negative
slack values. The first condition enables direct improvement
of
timing
quality without any extra optimization cost. The second condition
allows improvement
of
timing quality without using aggressive
optimization, so that the limitation on restructuring due to timing
exceptions may not affect the final timing quality. The third condition
is expected to reduce design area.
Ineffective timing exceptions. Some timing exceptions do not help
to reduce timing slack. In Figure 13, whether or not we define path A
as a false path, the timing slack for each timing point (all input/output
pins
of
cells, or primary ports)
of
the path will not change if the
path B is a true path and has tighter timing requirement (worse
timing slack) than path A. Therefore, adding a timing exception
for path A will only prevent restructuring that may be required for
path B to be optimized. Even if timing exceptions improve timing
slack, they can be regarded as ineffective if their timing improvement
is small and the timing slack is still critical, so that aggressive
timing optimization is required. In this case, timing degradation from
restrictions on optimization due to timing exceptions can outweigh
any timing improvement from the timing exceptions themselves.
To filter out ineffective timing exceptions from the generated
timing exceptions, we propose the following metrics - Maxlmp,
Sumlmp, Avglmp and
Endlmp
- to quantify the effectiveness
of
timing exceptions. Formally,
(I)
-.-
Critical FP
"""-
Critical Me p
100%50%25%
••
••
Non-critical M e p
10%
Number of timing exceptions
Maxlmp =
MaxC
EP(s~
- sc)
2:
U
rnax
••••••••••
••••••••••
•
•••••••••••
••••••••••
•• " ,. _ Non-critical FP
- -...- -
....
- - - * - - -.tt. -,
,
~
0%
-0.25
~
-0.2
g
~
-D.15
.::
~
-0.1
~
?!
-0.05
o
:;;
In summary, timing exceptions without "through" points reduce
timing slack and do not hurt optimization processes. By contrast,
timing exceptions with "through" points may help reduce timing
slack, but they limit the optimization (restructuring) solution space,
so that overall optimization quality is degraded for the paths specified
by such timing exceptions.
IV.
BEN
EFICIAL
TIMING
EXC
EPTIONS
Since a larger number
of
timing exceptions with "through" points
degrade the optimization quality, we wish to reduce the number
of
exceptions with "through" points. In other words, we have to audit
exceptions to obtain beneficial timing exceptions.
Fig. II . Restructured unit circuit
From the results, we observe that timing exceptions help reduce
timing violations for small numbers
of
stages, stage-I and stage-2,
compared to the results for no exceptions; however, the improvement
is quite small and not consistent. For large numbers
of
stages, stage-
4 and stage-8, the timing violations with false paths are worse than
those without false paths. In addition, for the stage-S case, runtime
increases excessively without improving timing compared to the case
of
no exceptions. When we apply MCP exceptions, QOR is improved.
Analysis
of
the circuit topology after optimization gives the same
conclusion as with the RCA example: when many false paths are
used, so that many "through" points are specified, restructuring is
limited and timing is degraded.
saCE
performs restructuring when
timing exceptions without "through" points are applied, as shown in
Column 3 (0% FP), and Column 7 (MCP) cases. Figure I I shows
the unit circuit as restructured by
saCE.
A. Critical Timing Exceptions
First, we examine the impact
of
critical exceptions (on negative
timing slack paths) and non-critical exceptions (on positive slack
paths) in the exception space (Figure 4). To compare the impact
of
critical and non-critical exceptions, we perform experiments with
four different kinds
of
exceptions - critical false paths, critical
multicycle paths, non-critical false paths and non-critical multicycle
paths. We select 10,000 exceptions and apply them in the incremental