Patent•
Methods and apparatus for extending the effective thermal operating range of a memory
29 Jun 2007-
TL;DR: In this article, a thermal sensor on a memory IC and a heating element coupled to the thermal sensor and adapted to heat the memory IC in response to a signal from the sensor are described.
Abstract: Systems, methods, and apparatus are provided for thermal regulation of a non-volatile memory IC. The systems and apparatus may include a thermal sensor on a memory IC; and a heating element coupled to the thermal sensor and adapted to heat the memory IC in response to a signal from the thermal sensor. The methods may include sensing a temperature of a memory IC using an integrated thermal sensor on the memory IC and heating the memory IC, using an integrated heating element operatively coupled to the thermal sensor, if the sensed temperature is below a threshold temperature.
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Patent•
11 Mar 2008TL;DR: In this article, a method for operating a memory that includes a plurality of analog memory cells was proposed, where first storage values were written to the cells and second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage value is estimated.
Abstract: A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.
324 citations
Patent•
30 Oct 2007
TL;DR: In this paper, a method for storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells of the memory by writing respective analog input values selected from a set of nominal values to the analog memory, is presented.
Abstract: A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.
282 citations
Patent•
10 May 2007TL;DR: In this paper, the second voltage levels are affected by cross-coupling interference causing the second voltages to differ from the respective first voltages, and the data stored in the group of analog memory cells is reconstructed from the read second voltage level using the estimated crosscoupled coefficients.
Abstract: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.
265 citations
Patent•
03 Dec 2007
TL;DR: In this paper, a method for storing data in a memory that includes analog memory cells was proposed, where the data is encoded using the selected ECC and the encoded data is stored in the group of the analog cells.
Abstract: A method for storing data in a memory (28) that includes analog memory cells (32) includes identifying one or more defective memory cells in a group of the analog memory cells. An Error Correction Code (ECC) is selected responsively to a characteristic of the identified defective memory cells. The data is encoded using the selected ECC and the encoded data is stored in the group of the analog memory cells. In an alternative method, an identification of one or more defective memory cells among the analog memory cells is generated. Analog values are read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells. The analog values are processed using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data.
262 citations
Patent•
10 May 2007
TL;DR: In this article, the second analog values are read from the respective memory cells of the memory device in which the encoded data were stored, and the second analogue values are processed using the error correction metrics in an ECC decoding process.
Abstract: A method for operating a memory device (24) includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells (32) of the memory device. After storing the encoded data, second analog values are read from the respective memory cells of the memory device in which the encoded data were stored. At least some of the second analog values differ from the respective first analog values. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.
260 citations
References
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Patent•
06 Dec 2002TL;DR: In this article, a very high density field programmable memory (FPM) is described. And the array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells.
Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
1,212 citations
Patent•
25 Apr 2001
TL;DR: In this paper, a multi-level memory array employing rail-stacks is described, which include a conductor and semiconductor layers, separated by an insulating layer used to form antifuses.
Abstract: A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.
528 citations
Patent•
17 Oct 1996
TL;DR: A read-only memory structure, having a three dimensional arrangement of memory elements, is described in this paper, where memory elements are partitioned into multiple memory levels and each memory level is stacked on top of another.
Abstract: A read-only memory structure, having a three dimensional arrangement of memory elements, is disclosed. The memory elements are partitioned into multiple memory levels. Each memory level is stacked on top of another. Within each memory level, there are a plurarity of memory elements and address select lines. The memory elements can be either mask programmable or electrical programmable.
439 citations
Patent•
07 Jun 1995TL;DR: In this article, a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element is described, which allows memory cells to be disposed every 0.7 microns or less across the face of a memory matrix.
Abstract: There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in a vertical stack between a wordline and digitline. The memory element is disposed in series with the diode, also between the wordline and the digitline. The diode is capable of delivering the large current flow required to program the memory element without also requiring the surface space on the upper surface of the memory matrix normally associated with such powerful diodes. The invention allows memory cells to be disposed every 0.7 microns or less across the face of a memory matrix. Further, the memory cell is easily fabricated using standard processing techniques. The unique layout of the inventive memory cell allows fabrication with as few as three mask steps or less.
439 citations
Patent•
24 Sep 1985TL;DR: In this article, a programmable device can be made with semiconductor layers which form two series coupled back-to-back diodes, each of which can be selectively programmed to lose its rectifying feature.
Abstract: A solid state semiconductor device is disclosed which is programmable so as to alter the impedance between its two terminals. In many embodiments, the device is programmable to have any one of four conditions: a first in which the electrical impedance is relatively high in both directions; a second in which the impedance is relatively high in one direction and relatively low in the opposite direction; a third in which the impedance is relatively high in the opposite direction and relatively low in the first direction; and a fourth in which the impedance is relatively low in both directions. Such a programmable device can be made with semiconductor layers which form two series coupled back-to-back diodes, each of which can be selectively programmed to lose its rectifying feature. Structures are disclosed which include a plurality of such programmable devices in one or more separately programmable planes, each with its own addressing means. Programmable logic arrays can be formed out of such multilayered cell structures, including programmable logic arrays, in which the AND and OR planes are vertically disposed one on top of the other.
397 citations