Dissertation•
Métodos y herramientas para el diseño a nivel de sistema de plataformas multiprocesador heterogéneas para multimedia
13 Apr 2011-
TL;DR: ESL as mentioned in this paper is a metodos de diseno a nivel de sistema (ESL) that can be used to improve the productividad de the disenadores and aliviar the tareas of diseno and verificacion of sistemas in un unico chip.
Abstract: Los metodos de diseno a nivel de sistema (ESL) estan siendo propuestos en la industria de los semiconductores como un complemento a las soluciones convencionales, con el objetivo de mejorar la productividad de los disenadores y aliviar las tareas de diseno y verificacion de sistemas en un unico chip. ESL se esta estableciendo rapidamente en la industria de los semiconductores gracias a los estandares SystemC y TLM2.0 (modelado a nivel de transacciones) que permiten elevar el nivel de abstraccion de los disenos por encima del tipico nivel a transferencia entre registros (RTL). Mas concretamente, ESL esta siendo aplicado en los flujos de diseno de forma exitosa por medio de prototipos virtuales (VP) descritos en SystemC y TLM. Los usos tipicos de un prototipo virtual estan en el desarrollo de software embebido antes de que un prototipo fisico del hardware este disponible o la exploracion de diversas alternativas de implementacion durante la fase de especificacion del chip, entre otros. El problema aparece cuando tenemos en cuenta que estos diferentes usos tipicos de un prototipo virtual tienen diferentes requisitos en terminos de velocidad de simulacion, precision en los resultados, etc., que hace muy dificil elegir un unico estilo para modelar un prototipo virtual de forma que cumpla todos los requisitos para todos los casos. Esta tesis doctoral tiene como mayores contribuciones metodos, herramientas y librerias de modelado a nivel de sistema que permiten reutilizar y refinar modelos entre los usos tipicos de un prototipo virtual, basandose enteramente en el estandar IEEE SystemC y el nuevo estandar de modelado TLM2.0 Mas concretamente las contribuciones se centran en dos pasos del proceso de refinamiento de los modelos: el paso de refinamiento de un modelo funcional a un modelo arquitectural y el paso de refinamiento gradual dentro de los modelos arquitecturales para anadir precision temporal.
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Journal Article•
TL;DR: General concepts enabling IP core re-use are required which shall act as foundation for platform based design and the aurhors introduce concepts such as IP-core/system abstraction and generic IP core interfacing.
Abstract: Large global semiconductors companies today face the challenge to enable the production of IP cores which are highly re-usable across the company. A widely known approach to tackle this issue is platform based System-On-Chip design for which application domain specific architecture templates and rules are imposed on the design of IP cores to ensure their applicability within the platform context. However, due to the convergence trend of digital technology for consumer products, certain IP core functions shall become applicable beyond a single platform context, which again leads to the challenge of re-usability. Instead of pure platform specific architectural concepts, general concepts enabling IP core re-use are required which shall act as foundation for platform based design. The aurhors introduce concepts such as IP-core/system abstraction and generic IP core interfacing. Furthermore an application example from product development is given.
11 citations
Dissertation•
18 May 2011
TL;DR: In this paper, the authors present a set of metodologias and novedosos algoritmos with el aim of aminorar el esfuerzo del disenador de sistemas and lograr eficientes DSE in la etapa temprana del proceso de diseno.
Abstract: A medida que la capacidad de integracion en chip aumenta, los sistemas en chip (SoC) se vuelven cada vez mas complejos, siendo bastante habitual en la actualidad encontrarnos con SoCs que integran una gran variedad de elementos de procesamiento, memorias, dispositivos I/O y elementos de comunicacion. Para hacer frente a la complejidad de diseno de los modernos SoCs, los disenadores de sistemas propusieron elevar el nivel de abstraccion del proceso de diseno al nivel de sistema, donde la exploracion del espacio de diseno (DSE) se ha convertido en una pieza clave en el proceso de diseno a nivel de sistema (SLD). Sin embargo, cabria preguntar en este contexto si las metodologias de diseno existentes permiten al disenador explotar todo el beneficio potencial de la DSE a nivel de sistema, o si se deberian plantear nuevas metodologias y/o tecnicas alternativas para sacar el maximo provecho del SLD. Esta tesis pretende precisamente responder a dicha cuestion. Concretamente, hemos desarrollo nuevas metodologias y novedosos algoritmos con el objetivo de aminorar el esfuerzo del disenador de sistemas y lograr eficientes DSE en la etapa temprana del proceso de diseno. Asimismo, con el fin de validar nuestras tecnicas y esquemas de trabajo, tambien hemos presentado una importante cantidad de experimentos de DSE en esta tesis. Estos resultados experimentales demuestran que, en comparacion con las metodologias tradicionales, nuestras propuestas no solo pueden mejorar la productividad del disenador y la eficiencia de DSE a nivel de sistema, sino que tambien son capaces de obtener soluciones de disenos de mayor calidad.
Cites background from "Métodos y herramientas para el dise..."
...Comparado con otras propuestas tradicionales (como FPGA o simulaciones RTL), un ESM que se crea siguiendo el principio de Y-Chart presenta varias ventajas: • El diseñador puede disponer del ESM en una fase muy temprana del proceso de diseño....
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...Therefore, other interesting future work would be to extend the NASA framework by adding additional capabilities such as gradual model refinement, automated synthesis, and RTL generation towards a defined target technology....
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...The Daedalus framework [68] also extends the work from Sesame by adding automatic application parallelization from sequential C/C++ description and automated synthesis and RTL integration towards FPGA technology....
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...En estos términos, CASSE debe proporcionar al menos un factor de mejora de x1000 con respecto a las simulaciones RTL si se desea obtener una mejora significativa en la DSE a nivel de sistema....
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...A diferencia de los tradicionales simuladores para RTL, estos nuevos simuladores trabajan a nivel de transacciones (TLM)....
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References
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Proceedings Article•
01 Jan 1974
TL;DR: A simple language for parallel programming is described and its mathematical properties are studied to make a case for more formal languages for systems programming and the design of operating systems.
Abstract: In this paper, we describe a simple language for parallel programming. Its semantics is studied thoroughly. The desirable properties of this language and its deficiencies are exhibited by this theoretical study. Basic results on parallel program schemata are given. We hope in this way to make a case for more formal (i.e. mathematical) approach to the design of languages for systems programming and the design of operating systems. There is a wide disagreement among systems designers as to what are the best primitives for writing systems programs. In this paper, we describe a simple language for parallel programming and study its mathematical properties. 1. A SIMPLE LANGUAGE FOR PARALLEL PROGRAMMING The features of our mini-language are exhibited on the sample program S on Figure 1. The conventions are close to Algol1 and we only insist upon the new features. The program S consists of a set of declarations and a body. Variables of type integer channel are declared at line (1), and for any simple type σ (boolean, real, etc. . . ) we could have declared a σ channel. Then processes f , g and h are declared, much like procedures. Aside from usual parameters (passed by value in this example, like INIT at line (3)), we can declare in the heading of the process how it is linked to other processes : at line (2) f is stated to communicate via two input lines that can carry integers, and one similar output line. The body of a process is an usual Algol program except for invocation of wait until something on an input line (e.g. at (4)) or send a variable on a line of compatible type (e.g. at (5)). The process stays blocked on a wait until something is being sent on this line by another process, but nothing can prevent a process from performing a send on a line. In others words, processes communicate via first-in first-out (fifo) queues. Calling instances of the processes is done in the body of the main program at line (6) where the actual names of he channels are bound to the formal parameters of the processes. The infix operator par initiates the concurrent activation of the processes. Such a style of programming is close to may systems using EVENT mechanisms ([1, 2, 3, 4]). A pictorial representation of the program is the schema P on Figure 2, where the nodes represent processes and the arcs communication channels between these processes. What sort of things would we like to prove on a program like S? Firstly, that all processes in S run forever. Secondly, Begin (1) In t eg e r channel X, Y, Z , T1 , T2 ; (2 ) Process f ( i n t e r g e r in U,V; i n t e r g e r out W) ; Begin i n t e g e r I ; l o g i c a l B; B := true ; Repeat Begin (4 ) I := i f B then wait (U) e l s e wait (V) ; (7 ) p r in t ( I ) ; (5 ) send I on W; B := not B; End ; End ; Process g ( i n t e g e r in U ; i n t e g e r out V, W) ; Begin i n t e g e r I ; l o g i c a l B; B := true ; Repeat Begin I := wait (U) ; i f B then send I on V e l s e send I on W : B := not B; End ; End ; (3 ) Process h( i n t e g e r in U; i n t e g e r out V; i n t e g e r INIT ) ; Begin i n t e g e r I ; send INIT on V; Repeat Begin I := wait (U) ; send I on V; End ; End ; Comment : body o f mainprogram ; (6 ) f (X,Y,Z) par g (X,T1 ,T2) par h(T1 ,Y, 0 ) par h(T2 , Z , 1 ) ; End ; Figure 1: Sample parallel program S. more precisely, that S prints out (at line (7)) an alternating sequence of 0’s and 1’s forever. Third, that if one of the processes were to stop at some time for an extraneous reason, the whole systems would stop. The ability to state formally this kind of property of a parallel program and to prove them within a formal logical framework is the central motivation for the theoretical study of the next sections. 2. PARALLEL COMPUTATION Informally speaking, a parallel computation is organized in the following way: some autonomous computing stations are connected to each other in a network by communication lines. Computing stations exchange information through these lines. A given station computes on data coming along
2,478 citations
Book•
31 May 2002
TL;DR: System Design and SystemC provides a comprehensive introduction to the powerful modeling capabilities of the SystemC language, and also provides a large and valuable set of system level modeling examples and techniques.
Abstract: The emergence of the system-on-chip (SoC) era is creating many new challenges at all stages of the design process. Engineers are reconsidering how designs are specified, partitioned and verified. With systems and software engineers programming in C/C++ and their hardware counterparts working in hardware description languages such as VHDL and Verilog, problems arise from the use of different design languages, incompatible tools and fragmented tool flows. Momentum is building behind the SystemC language and modeling platform as the best solution for representing functionality, communication, and software and hardware implementations at various levels of abstraction. The reason is clear: increasing design complexity demands very fast executable specifications to validate system concepts, and only C/C++ delivers adequate levels of abstraction, hardware-software integration, and performance. System design today also demands a single common language and modeling foundation in order to make interoperable system--level design tools, services and intellectual property a reality. SystemC is entirely based on C/C++ and the complete source code for the SystemC reference simulator can be freely downloaded from www.systemc.org and executed on both PCs and workstations. System Design and SystemC provides a comprehensive introduction to the powerful modeling capabilities of the SystemC language, and also provides a large and valuable set of system level modeling examples and techniques. Written by experts from Cadence Design Systems, Inc. and Synopsys, Inc. who were deeply involved in the definition and implementation of the SystemC language and reference simulator, this book will provide you with the key concepts you need to be successful with SystemC. System Design with SystemC thoroughly covers the new system level modeling capabilities available in SystemC 2.0 as well as the hardware modeling capabilities available in earlier versions of SystemC. designed and implemented the SystemC language and reference simulator, this book will provide you with the key concepts you need to be successful with SystemC. System Design with SystemC will be of interest to designers in industry working on complex system designs, as well as students and researchers within academia. All of the examples and techniques described within this book can be used with freely available compilers and debuggers e no commercial software is needed. Instructions for obtaining the free source code for the examples obtained within this book are included in the first chapter.
1,011 citations
TL;DR: This work defines system platforms and argues about their use and relevance, and presents a new approach to platform-based design called modern embedded systems, compilers, architectures and languages, based on highly concurrent and software programmable architectures and associated design tools.
Abstract: System-level design issues become critical as implementation technology evolves toward increasingly complex integrated circuits and the time-to-market pressure continues relentlessly. To cope with these issues, new methodologies that emphasize re-use at all levels of abstraction are a "must", and this is a major focus of our work in the Gigascale Silicon Research Center. We present some important concepts for system design that are likely to provide at least some of the gains in productivity postulated above. In particular, we focus on a method that separates parts of the design process and makes them nearly independent so that complexity could be mastered. In this domain, architecture-function co-design and communication-based design are introduced and motivated. Platforms are essential elements of this design paradigm. We define system platforms and we argue about their use and relevance. Then we present an application of the design methodology to the design of wireless systems. Finally, we present a new approach to platform-based design called modern embedded systems, compilers, architectures and languages, based on highly concurrent and software programmable architectures and associated design tools.
886 citations
01 Oct 2003
TL;DR: A TLM taxonomy is introduced and the benefits of TLMs' use in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is compared.
Abstract: Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models (TLMs) are not well defined and the usage of TLMs in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is not well coordinated. This paper introduces a TLM taxonomy and compares the benefits of TLMs' use.
611 citations
TL;DR: Based on a metamodel with formal semantics that developers can use to capture designs, Metropolis provides an environment for complex electronic-system design that supports simulation, formal analysis, and synthesis.
Abstract: Today, the design chain lacks adequate support, with most system-level designers using a collection of unlinked tools. The implementation then proceeds with informal techniques involving numerous human-language interactions that create unnecessary and unwanted iterations among groups of designers in different companies or different divisions. The move toward programmable platforms shifts the design implementation task toward embedded software design. When embedded software reaches the complexity typical of today's designs, the risk that the software will not function correctly increases exponentially. The Metropolis project seeks to develop a unified framework that can cope with this challenge. Based on a metamodel with formal semantics that developers can use to capture designs, Metropolis provides an environment for complex electronic-system design that supports simulation, formal analysis, and synthesis.
549 citations