Microprocessor Software-Based Self-Testing

doi:10.1109/MDT.2010.5

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Microprocessor Software-Based Self-Testing

Journal Article•DOI•

Microprocessor Software-Based Self-Testing

Mihalis Psarakis¹, Dimitris Gizopoulos¹, Ernesto Sanchez, Matteo Sonza Reorda•Institutions (1)

University of Piraeus¹

01 May 2010-IEEE Design & Test of Computers (IEEE)-Vol. 27, Iss: 3, pp 4-19

TL;DR: A taxonomy for different SBST methodologies according to their test program development philosophy is proposed, and research approaches based on SBST techniques for optimizing other key aspects are summarized.

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Abstract: This article discusses the potential role of software-based self-testing in the microprocessor test and validation process, as well as its supplementary role in other classic functional- and structural-test methods. In addition, the article proposes a taxonomy for different SBST methodologies according to their test program development philosophy, and summarizes research approaches based on SBST techniques for optimizing other key aspects.

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Proceedings Article•DOI•

Architectures for online error detection and recovery in multicore processors

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Dimitris Gizopoulos¹, Mihalis Psarakis¹, Sarita V. Adve², Pradeep Ramachandran², Siva Kumar Sastry Hari², Daniel J. Sorin³, Albert Meixner³, Arijit Biswas⁴, Xavier Vera⁴ - Show less +5 more•Institutions (4)

University of Piraeus¹, University of Illinois at Urbana–Champaign², Duke University³, Intel⁴

14 Mar 2011

TL;DR: This paper focuses on dependable multicore processor architectures that integrate solutions for online error detection, diagnosis, recovery, and repair during field operation and discusses taxonomy of representative approaches and presents a qualitative comparison based on hardware cost, performance overhead, types of faults detected, and detection latency.

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Abstract: The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chips. Extremely complex, massively parallel, multi-core processor chips fabricated in these technologies will become more vulnerable to: (a) environmental disturbances that produce transient (or soft) errors, (b) latent manufacturing defects as well as aging/wearout phenomena that produce permanent (or hard) errors, and (c) verification inefficiencies that allow important design bugs to escape in the system. In an effort to cope with these reliability threats, several research teams have recently proposed multicore processor architectures that provide low-cost dependability guarantees against hardware errors and design bugs. This paper focuses on dependable multicore processor architectures that integrate solutions for online error detection, diagnosis, recovery, and repair during field operation. It discusses taxonomy of representative approaches and presents a qualitative comparison based on: hardware cost, performance overhead, types of faults detected, and detection latency. It also describes in more detail three recently proposed effective architectural approaches: a software-anomaly detection technique (SWAT), a dynamic verification technique (Argus), and a core salvaging methodology.

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122 citations

Additional excerpts

...Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera...
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Journal Article•DOI•

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

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Paolo Bernardi¹, Riccardo Cantoro¹, Sergio De Luca², Ernesto Sanchez¹, A. Sansonetti² - Show less +1 more•Institutions (2)

Polytechnic University of Turin¹, STMicroelectronics²

01 Mar 2016-IEEE Transactions on Computers

TL;DR: This paper illustrates the several issues that need to be taken into account when generating test programs for on-line execution and proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts.

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Abstract: Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts; (3) it is providing guidelines for allowing the coexistence of the Core Self-Test library with the mission application while guaranteeing execution robustness. The proposed methodology has been experimented on a large industrial case study. The coverage level reached after one year of team work is over 87 percent of stuck-at fault coverage, and execution time is compliant with the ISO26262 specification. Experimental results suggest that alternative approaches may request excessive evaluation time thus making the generation flow unfeasible for large designs.

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67 citations

Cites background from "Microprocessor Software-Based Self-..."

...Built-In Self-Test (BIST), it presents many advantages, such as: the possibility of autonomously testing [5] and diagnosing [6] both the microprocessor and the controllable peripherals; working in normal mode of operation; not requiring any hardware modifications; allowing at-speed test application (i....
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Proceedings Article•DOI•

A Reliability Analysis of a Deep Neural Network

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Alberto Bosio¹, Paolo Bernardi², Annachiara Ruospo², Ernesto Sanchez²•Institutions (2)

École centrale de Lyon¹, Polytechnic University of Turin²

11 Mar 2019

TL;DR: This work presents a method-ology to evaluate the impact of permanent faults affecting CNN exploited for automotive applications through a fault injection enviroment built upon on the darknet open source DNN framework.

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Abstract: Deep Learning, and in particular its implementation using Convolutional Neural Networks (CNNs), is currently one of the most intensively and widely used predictive models for safety-critical applications like autonomous driving assistance on pedestrian, objects and structures recognition. Today, ensuring the reliability of these innovations is becoming very important since they involve human lives. One of the peculiarities of the CNNs is the inherent resilience to errors due to the iterative nature of the learning process. In this work we present a method-ology to evaluate the impact of permanent faults affecting CNN exploited for automotive applications. Such a characterization is performed through a fault injection enviroment built upon on the darknet open source DNN framework. Results are shown about fault injection campaigns where permanent faults are affecting the connection weights in the LeNet and Yolo; the behavior of the corrupted CNN is classified according to the criticality of the introduced deviation.

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64 citations

Cites background from "Microprocessor Software-Based Self-..."

...g, Software-based Self-test [8]), or a combination of both....
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Journal Article•DOI•

A Flexible Framework for the Automatic Generation of SBST Programs

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Andreas Riefert¹, Riccardo Cantoro², Matthias Sauer¹, Matteo Sonza Reorda², Bernd Becker¹ - Show less +1 more•Institutions (2)

University of Freiburg¹, Polytechnic University of Turin²

01 Oct 2016-IEEE Transactions on Very Large Scale Integration Systems

TL;DR: The proposed method is the first approach able to automatically generate SBST programs for both end- of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.

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Abstract: Software-based self-test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.

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45 citations

Cites methods from "Microprocessor Software-Based Self-..."

...When processors are considered, functional test typically takes the form of software-based self-test (SBST) [1]: the processor is forced to execute a given test program, and faults are detected by looking at the results produced by the program (e....
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Journal Article•DOI•

Test Strategies for Reliable Runtime Reconfigurable Architectures

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Lars Bauer¹, Claus Braun², Michael E. Imhof², Michael A. Kochte², Eric Schneider², Hongyan Zhang¹, Jorg Henkel¹, Hans-Joachim Wunderlich² - Show less +4 more•Institutions (2)

Karlsruhe Institute of Technology¹, University of Stuttgart²

01 Aug 2013-IEEE Transactions on Computers

TL;DR: Experimental results show that the integration of online testing in reconfigurable systems incurs only minimum impact on performance while delivering high fault coverage and low test latency.

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Abstract: Field-programmable gate array (FPGA)-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well as aging effects and latent defects. To ensure reliable reconfiguration, it is mandatory to guarantee the correct operation of the reconfigurable fabric. This can be achieved by periodic or on-demand online testing. This paper presents a reliable system architecture for runtime-reconfigurable systems, which integrates two nonconcurrent online test strategies: preconfiguration online tests (PRET) and postconfiguration online tests (PORT). The PRET checks that the reconfigurable hardware is free of faults by periodic or on-demand tests. The PORT has two objectives: It tests reconfigured hardware units after reconfiguration to check that the configuration process completed correctly and it validates the expected functionality. During operation, PORT is used to periodically check the reconfigured hardware units for malfunctions in the programmable logic. Altogether, this paper presents PRET, PORT, and the system integration of such test schemes into a runtime-reconfigurable system, including the resource management and test scheduling. Experimental results show that the integration of online testing in reconfigurable systems incurs only minimum impact on performance while delivering high fault coverage and low test latency.

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34 citations

Cites methods from "Microprocessor Software-Based Self-..."

...The regions of the reconfigurable fabric that are not intended for runtime reconfiguration can be tested for permanent faults with established approaches such as software-based testing of processors and caches [16], or periodic FPGA test methods that require the interruption of operation [17]....
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References

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Journal Article•DOI•

Test Generation for Microprocessors

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Thatte¹, Abraham²•Institutions (2)

Texas Instruments¹, University of Illinois at Urbana–Champaign²

01 Jun 1980-IEEE Transactions on Computers

TL;DR: In this paper, a general graph-theoretic model is developed at the register transfer level which takes the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model.

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Abstract: The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.

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380 citations

Proceedings Article•DOI•

FRITS - a microprocessor functional BIST method

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Praveen Parvathala¹, Kailasnath Maneparambil¹, W. Lindsay¹•Institutions (1)

Intel¹

07 Oct 2002

TL;DR: A novel functional Built-in-Self-Test (BIST) method for microprocessors is described, based on the fundamental principle that complex chips have embedded functionality that can be used to implement a comprehensive self-test strategy.

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Abstract: This paper describes a novel functional Built-in-Self-Test (BIST) method for microprocessors. This technique is based on the fundamental principle that complex chips have embedded functionality that can be used to implement a comprehensive self-test strategy. Functional testing has generally been associated with expensive testers. In order to lower the cost of test, there is a general trend to adopt structural test techniques like scan that enable the use of low cost testers. One of the key advantages of the test method described here is that it enables functional testing of microprocessors on low cost testers. Detailed implementation of this technique, the test generation methodology, the fault grade methodology and silicon results on Intel/sup /spl reg// Pentium/sup /spl reg// 4 and Itanium/spl trade/ family microprocessors are presented.

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231 citations

"Microprocessor Software-Based Self-..." refers background or methods in this paper

...SBST has become more accepted for microprocessor testing, and it already forms an integral part of the manufacturing test flow for major processor vendors.(2,3) This article is the first attempt at classifying SBST approaches according to the way they generate self-test programs....
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...The approaches of Parvathala, Maneparambil, and Lindsay (Intel) and Bayraktaroglu, Hunt, and Watkins (Sun) provide strong evidence of the usefulness of SBST in the manufacturing flow of industrial processor designs.(2,3) Unlike the previously described functional methods, the method proposed by Corno et al....
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...Parvathala, Maneparambil, and Lindsay have presented an automated functional self-test method called Frits (Functional Random Instruction Testing at Speed), which generates random instruction sequences with pseudorandom data.(2) In this paper, the basic requirements for the application of a cache-resident approach have been determined....
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...The first corresponds to methods that rely mainly on code randomizers (possibly oriented with suitable constraints) to obtain test programs.(2,3,6) The second consists of methods that adopt a feedbackbased strategy,(7) meaning they evaluate generated test programs according to suitable metrics (often computed through simulation) and try to progressively improve them....
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...Some of the approaches have already been applied in industrial test flows for example, in the manufacturingtest process of Intel’s Pentium 4 and Itanium processors and Sun’s UltraSparc T1 processor.(2,3) For others, the real applicability must still be evaluated in morecomplex processors in terms of development cost (human effort and computational resources) and test efficiency (coverage for different fault models)....
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Journal Article•DOI•

Software-based self-testing of embedded processors

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N. Kranitis¹, Antonis Paschalis¹, Dimitris Gizopoulos, G. Xenoulis²•Institutions (2)

Athens State University¹, University of Piraeus²

01 Apr 2005-IEEE Transactions on Computers

TL;DR: This paper presents a high-level, functional component-oriented, software-based self-testing methodology for embedded processors and validate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture.

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Abstract: Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.

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188 citations

"Microprocessor Software-Based Self-..." refers background or methods in this paper

...N. Kranitis et al., ‘‘Software-Based Self-Testing of Embedded Processors,’’ IEEE Trans....
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...The methods proposed by Rizk, Papachristou, and Wolff and Krstic et al. fall into this category.14,16 Kranitis et al. have proposed a component-based divide-and-conquer approach.12 Program generation is based only on the processor ISA and its RTL description....
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...fall into this category.(12,13) ATPG algorithms generate test stimuli starting from a gate-level description of the module....
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...have proposed a component-based divide-and-conquer approach.(12) Program generation is based only on the processor ISA and its RTL description....
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...They first identify the testability hotspots of the pipelining logic, applying existing SBST programs (generated according to the methodology by Kranitis et al.(12) and targeting the processor’s functional components) to two fully pipelined RISC processor models: miniMIPS and OpenRISC 1200....
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Proceedings Article•DOI•

Native mode functional test generation for processors with applications to self test and design validation

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Jian Shen, Jacob A. Abraham

18 Oct 1998

TL;DR: This work presents a versatile automatic functional test generation methodology for microprocessors that can be applied to both design validation and manufacturing test, especially in high speed "native" mode.

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Abstract: New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. We present a versatile automatic functional test generation methodology for microprocessors. The generated assembly instruction sequences can be applied to both design validation and manufacturing test, especially in high speed "native" mode. All the functional capabilities of complex processors can be exercised, leading to high quality validation sequences and manufacturing tests with high fault coverage. The tests can also be applied in a built-in self-test fashion. Experimental results on two microprocessors show that this method is very effective in generating high quality manufacturing tests as well as in functional design validation.

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163 citations

"Microprocessor Software-Based Self-..." refers background or methods in this paper

...Shen and Abraham have used a tool named Vertis, which can generate both test and verification programs on the basis of only the processor’s ISA.6 Vertis generates many different instruction sequences for every instruction tested....
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...Shen and Abraham have used a tool named Vertis, which can generate both test and verification programs on the basis of only the processor’s ISA.(6) Vertis generates many different instruction sequences for every instruction tested....
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...Functional approaches can be easily integrated in any processor design flow because they are based only on the ISA and don’t require sophisticated test development or experienced test engineers.(2,3,6,7) Their basic limitation is that they cannot achieve high structural-fault coverage because they don’t consider the processor structure....
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...The first corresponds to methods that rely mainly on code randomizers (possibly oriented with suitable constraints) to obtain test programs.(2,3,6) The second consists of methods that adopt a feedbackbased strategy,(7) meaning they evaluate generated test programs according to suitable metrics (often computed through simulation) and try to progressively improve them....
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Proceedings Article•DOI•

A scalable software-based self-test methodology for programmable processors

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Li Chen¹, Srivaths Ravi², Anand Raghunathan², Sujit Dey¹•Institutions (2)

University of California, San Diego¹, Princeton University²

02 Jun 2003

TL;DR: Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.

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Abstract: Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/output mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/output mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software self-test program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/output mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors. To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa form Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.

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130 citations

"Microprocessor Software-Based Self-..." refers background in this paper

...and Wen, Wang, and Cheng extract information about the circuit surrounding the module under consideration.(10,11) In the approach proposed by Chen et al....
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...For example, using different techniques, the methods presented by Chen et al. and Wen, Wang, and Cheng extract information about the circuit surrounding the module under consideration.10,11 In the approach proposed by Chen et al.,10 the processor is first partitioned into a set of modules....
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...The methods proposed by Chen et al. and Krstic et al. belong to this category.15,16 Pseudorandom methods randomly generate sequences of instructions and/or data to be internally elaborated by the processor....
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...Chen et al. have described a two-step test-program generation methodology that uses multiple-level abstractions of the processor under consideration, including the ISA description, RTL model, architectural model, and synthesized gate-level netlist.15 In the first phase, processor classification identifies ISA registers, logic and control blocks, pipelined registers, and pipeline-related control logic....
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...Hierarchical structural approaches based on constrained test generation avoid the exponential growth of test generation complexity by using simulationbased learning to describe the circuit at higher abstraction levels.(10,11) However, their test efficiency depends on the quality of the instruction templates and learned models, which cannot be guaranteed....
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