Microprocessors and microsystems
01 Jan 1978-
About: The article was published on 1978-01-01 and is currently open access. It has received 131 citations till now.
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TL;DR: The MorphoSys architecture is described, including the reconfigurable processor array, the control processor, and data and configuration memories, and the suitability of MorphoSy for the target application domain is illustrated with examples such as video compression, data encryption and target recognition.
Abstract: This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.
895 citations
Book•
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01 Jan 1986
TL;DR: The transputer architecture, a programmable VLSI component with communication links for point-to-point connection to other transputers, provides the same concurrent programming techniques both for a single transputer and for a network of transputers.
138 citations
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...An important design objective of oecam and the transputer was to provide the same concurrent programming techniques both for a single transputer and for a network of transputers....
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TL;DR: It is hoped that this implementation and fixed-point error analysis will lead to a better understanding of the issues involved in finite register length implementation of the discrete fractional Fourier transform and will help the signal processing community make better use of the transform.
128 citations
TL;DR: A platform for evolving spiking neural networks on FPGAs is presented as a combination of three parts: a hardware substrate, a computing engine, and an adaptation mechanism.
117 citations
TL;DR: It is demonstrated how the removal of the clock secures a potential point of attack and enables additional fine-grain timing countermeasures to be introduced in smart card functions that are resistant to both side-channel and fault injection attacks.
100 citations
References
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TL;DR: The MorphoSys architecture is described, including the reconfigurable processor array, the control processor, and data and configuration memories, and the suitability of MorphoSy for the target application domain is illustrated with examples such as video compression, data encryption and target recognition.
Abstract: This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.
895 citations
TL;DR: It is hoped that this implementation and fixed-point error analysis will lead to a better understanding of the issues involved in finite register length implementation of the discrete fractional Fourier transform and will help the signal processing community make better use of the transform.
128 citations
TL;DR: A platform for evolving spiking neural networks on FPGAs is presented as a combination of three parts: a hardware substrate, a computing engine, and an adaptation mechanism.
117 citations
TL;DR: It is demonstrated how the removal of the clock secures a potential point of attack and enables additional fine-grain timing countermeasures to be introduced in smart card functions that are resistant to both side-channel and fault injection attacks.
100 citations
TL;DR: This work develops a stream-oriented compute model, system architecture, and execution patterns which can capture and exploit the parallelism of spatial computations while simultaneously abstracting software applications from hardware details and consequently allowing applications to scale to exploit newer, larger, and faster hardware platforms.
91 citations