Patent•
Microstructure device comprising a face to face electromagnetic near field coupling between stacked device portions and method of forming the device
03 Apr 2012-
TL;DR: In this article, a galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration, which can be fabricated on any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.
Abstract: A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.
Citations
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Patent•
29 Jun 2011
TL;DR: In this paper, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the die or non-coplanarity of contacts.
Abstract: In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.
112 citations
TL;DR: This paper presents a galvanically isolated power transfer system based on two inductively coupled CMOS oscillators with on-chip isolation transformer that performs the combining of the oscillation signals at its secondary winding output.
Abstract: This paper presents a galvanically isolated power transfer system based on two inductively coupled CMOS oscillators with on-chip isolation transformer. The oscillators share the same current and are loaded by an integrated transformer that performs the combining of the oscillation signals at its secondary winding output. By using a thick inter-metal oxide layer for the integrated transformer, a galvanic isolation rating as high as 5 kV is guaranteed. Thanks to the proposed circuit topology, a 300-mW dc-ac power conversion performance with an excellent 36.5% power efficiency was achieved in a 0.8- $\mu{\rm m}$ CMOS technology at 5-V power supply. A complete dc-dc converter was also demonstrated by including a rectifier on a second die. An output power of 200 mW at 8-V output voltage with power efficiency better than 27% was measured.
29 citations
Patent•
20 Apr 2012TL;DR: In this paper, a method for producing a rounded conductor line of a semiconductor component is described, in which the bottom side and the top side are arranged in a vertical direction.
Abstract: A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.
23 citations
Patent•
25 Feb 2015TL;DR: In this paper, a transformer has a primary winding coupling the first oscillator circuit to the second oscillator circuits and a secondary winding, and the secondary winding is magnetically coupled with the primary winding so the secondary circuit receives an output power and an incoming high speed data transmission based upon the amplitude modulated data signal.
Abstract: An apparatus includes first and second oscillator circuits. A transformer has a primary winding coupling the first oscillator circuit to the second oscillator circuit and a secondary winding. A first outgoing communications circuit is coupled to the second oscillator circuit and drives an amplitude modulated data signal thereto. A first incoming communications circuit is coupled to the primary winding of the transformer. A second outgoing communications circuit is coupled to the secondary winding drives an amplitude modulated data signal thereto. A second incoming communications circuit is coupled to the secondary winding. The secondary winding is magnetically coupled with the primary winding so the secondary winding receives an output power and an incoming data transmission based upon the amplitude modulated data signal, and so the primary winding receives an incoming high speed data transmission based upon the amplitude modulated data signal.
15 citations
Patent•
14 Jul 2011
TL;DR: In this paper, an illumination system comprising a plurality of power strings features elements facilitating compensation for failure of one or more light-emitting elements connected along each power string, in accordance with certain embodiments.
Abstract: In accordance with certain embodiments, an illumination system comprising a plurality of power strings features elements facilitating compensation for failure of one or more light-emitting elements connected along each power string.
13 citations
References
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Patent•
24 Nov 1999TL;DR: In this paper, a method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopant into the substrate.
Abstract: A method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopants into the substrate, and forming a dielectric layer on a resultant structure to fill the entrance of the trenches, thereby forming air-gap layers inside the trenches, thereby reducing a parasitic capacitance and a magnetic coupling.
44 citations
Patent•
18 Jan 2010TL;DR: In this article, a signal transmission arrangement is disclosed for a voltage converter and a voltage amplifier, and the voltage converter includes a signal-to-noise ratio is calculated. But the signal transmission scheme is not discussed.
Abstract: A signal transmission arrangement is disclosed A voltage converter includes a signal transmission arrangement
27 citations
Patent•
02 Sep 2010TL;DR: In this paper, a first inductor and a second inductor are overlapped with each other in a direction in which a first multilayer interconnect layer is opposed to each other.
Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.
25 citations
Patent•
28 Apr 2009TL;DR: In this article, a method for forming a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate was proposed, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an interior layer crossed by conductive vias, the vias connecting a metal tracks of the interconnect stacks to the conductive regions.
Abstract: A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an insulating layer crossed by conductive vias, the vias connecting a metal track of the interconnect stack to the conductive region; gluing the external surface of the interconnect stack on a support and thinning down the substrate; etching the external surface of the thinned-down substrate and stopping on the insulating region; etching the insulating region and stopping on the conductive region; and filling the etched opening with a metal.
16 citations
Patent•
23 Mar 2009
TL;DR: In this article, a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor element and for supporting the inductor pattern and the SINR elements being arranged opposedly in an electrically isolated state are provided on a surface of the device layer of at least one of the elements.
Abstract: In a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor elements and for supporting the inductor patterns and the semiconductor elements being arranged opposedly in an electrically isolated state are provided on a surface of the device layer of at least one of semiconductor elements and an electrically insulating material is filled in a space between opposing surfaces of the semiconductor elements.
10 citations