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Journal ArticleDOI

Miller and noise effects in a synchronizing flip-flop

C. Dike1, Edward A. Burton1
01 Jun 1999-IEEE Journal of Solid-state Circuits (IEEE)-Vol. 34, Iss: 6, pp 849-855
TL;DR: In this paper, the effects of Miller coupling and thermal noise on a synchronizing flip-flop are described and a worst case mean-time-between-failure bound is established.
Abstract: The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.
Citations
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Proceedings Article
01 Jan 2009
TL;DR: A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput.
Abstract: A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (V CC ) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal V CC or at least 17% V CC reduction at equal throughput, corresponding to 31%-37% total power reduction.

328 citations


Cites background or methods from "Miller and noise effects in a synch..."

  • ...With this unique characteristic, the error path behaves similar to a traditional synchronizer circuit [12]–[14] with the exception of having combinational logic between the sequentials....

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  • ...During metastability, the CLK-to-Q delay push-out exponentially depends on the relationship between the setup time and the input data arrival time [12]–[14]....

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  • ...For DSTB and RFF, the mean time between inducing metastability on PIPELINE ERROR from one EDS circuit in a pipeline stage is calculated as [12]–[14]:...

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  • ...As modeled in (3) and (4), the extra logic between the sequentials exponentially reduces [12]–[14]....

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Journal ArticleDOI
TL;DR: In this article, a 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path activation probabilities for maximizing throughput.
Abstract: A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal VCC or at least 17% VCC reduction at equal throughput, corresponding to 31%-37% total power reduction.

321 citations

Proceedings ArticleDOI
12 May 2003
TL;DR: This paper reviews a number of cases of synchronization errors, analyzes the causes of the errors, and offers a correct synchronizer circuit for each case.
Abstract: Transferring data between mutually asynchronous clock domains requires safe synchronization. However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get "optimized" to the point where they do no longer operate correctly. This paper reviews a number of such cases, analyzes the causes of the errors, and offers a correct synchronizer circuit for each case. A correct two flop synchronizer is presented. After discussing cases that avoid synchronization, the following synchronizers are reviewed: one flop, sneaky path, greedy path, wrong protocol, global reset, async clear, DFT leakage, pulse, slow-to-fast, metastability blocker, parallel and shared flop synchronizers.

217 citations


Cites background from "Miller and noise effects in a synch..."

  • ...However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get “optimized” to the point where they do no longer operate correctly....

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  • ...The settling window T (namely the time separation between the two clock inputs to the two flops of the synchronizers) could be a whole clock cycle or a fraction thereof, and could be different for each side, as long as the desired reliability is obtained....

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  • ...The operation of synchronization circuits has been recognized for a long time as being delicate and easy to disturb [1-3, 7-12], but at the same time robust synchronizer design does guarantee safe operation for all practical purposes....

    [...]

Journal ArticleDOI
18 Jun 2007
TL;DR: A metastability-based true random number generator that achieves high entropy and passes NIST randomness tests, and a qualifier module grades the individual metastable events to produce a high-entropy random bit-stream.
Abstract: We present a metastability-based true random number generator that achieves high entropy and passes NIST randomness tests. The generator grades the probability of randomness regardless of the output bit value by measuring the metastable resolution time. The system determines the original random noise level at the time of metastability and tunes itself to achieve a high probability of randomness. Dynamic control enables the system to respond to deterministic noise and a qualifier module grades the individual metastable events to produce a high-entropy random bit-stream. The grading module allows the user to trade off output bit-rate with the quality of the bit-stream. A fully integrated true random number generator was fabricated in a 0.13 mum bulk CMOS technology with an area of 0.145 mm2.

165 citations


Cites background from "Miller and noise effects in a synch..."

  • ...In the metastable region, the resolution time can be modeled as , where and are device and circuit dependent constants, is the final voltage difference of the latch nodes and is the initial voltage difference from the metastable point [ 6 ]....

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Journal ArticleDOI
TL;DR: This tutorial provides a glimpse into the theory and practice of metastability, which can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value.
Abstract: Metastability can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value. Synchronizer circuits, which guard against metastability, are becoming ubiquitous with the proliferation of timing domains on a chip. Despite the critical importance of reliable synchronization, this topic remains inadequately understood. This tutorial provides a glimpse into the theory and practice of this fascinating subject.

149 citations

References
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Journal ArticleDOI
TL;DR: In this article, the authors used the AC small-signal analysis in the frequency domain instead of the usual time-domain approach to obtain the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops.
Abstract: Optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops are obtained by using the AC small-signal analysis in the frequency domain instead of the usual time-domain approach. The Miller effect on the metastability is investigated for the configurations which have a better metastable resolving capability. The mean time between failure (MTBF) was measured, and the result verifies this new design approach. The power supply disturbance and temperature variation effects on the metastability were also measured, and the data show that a 0.75-V change of power supply voltage and 75 degrees C change of chip temperature cause a four orders of magnitude difference in the MTBF. The simulation results using the AC small-signal frequency-domain analysis agree well with the measurement data for the different power supply voltages and chip temperatures, confirming that an AC small-signal approach can be used more widely for the design of metastable hardened latch/flip-flops. The other parameters are discussed in terms of their effects on the latch/flip-flop's susceptibility to the metastable state. >

110 citations


"Miller and noise effects in a synch..." refers methods in this paper

  • ...This has been demonstrated to be a reasonable first approach for device sizing by Flannagan [1], and again by Kim and Dutton [ 2 ]....

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Journal ArticleDOI
S.T. Flannagan1
TL;DR: In this article, the synchronization performance of CMOS circuits is examined theoretically and experimentally, and the phase characteristics of metastability are identified, and experimental measurements of error rate are made on a CMOS test circuit and the gain-bandwidth product for the circuit is determined.
Abstract: The synchronization performance of CMOS circuits is examined theoretically and experimentally. Criteria for maximizing CMOS gain are determined and are then compared with NMOS gain curves. The phase characteristics of metastability are identified. Experimental measurements of error rate are made on a CMOS test circuit, and the gain-bandwidth product for the circuit is determined from these data.

46 citations


"Miller and noise effects in a synch..." refers methods in this paper

  • ...This has been demonstrated to be a reasonable first approach for device sizing by Flannagan [ 1 ], and again by Kim and Dutton [2]....

    [...]

Journal ArticleDOI
J. Jex1, C. Dike1
TL;DR: In this paper, the authors describe the design, testing, and application of a BiNMOS metastability resolving synchronizer, which reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle.
Abstract: The design, testing, and application of a BiNMOS metastability resolving synchronizer is described. High speed signaling requires multiple clock cycle metastability settling time. The integrated circuit provides low tau (fast resolution) and is considered one of the fastest synchronizers available to date. The circuit reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle. High gain-bandwidth product is accomplished with n-p-n transistors driving a cross-coupled inverter latch with reduced node capacitance. Longer settling time is provided by omitting metastability immune circuitry and using a parallel staged synchronizer. >

31 citations


"Miller and noise effects in a synch..." refers background or methods in this paper

  • ...Our experience has been that the deterministic line is usually less steep than the slope of the true metastability region [ 3 ]....

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  • ...Using this method insured that any data transition that caused a transition on the output of the DUT occurred within 3 ns of the clock edge [ 3 ]....

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  • ...The second region of interest is from 0 to about 110 ps. We have coined the term “deterministic region” to describe this portion of the curve because the output transition is delayed from a normal propagation but its delay is determined by the setup time [ 3 ]....

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