Miller and noise effects in a synchronizing flip-flop
Citations
328 citations
Cites background or methods from "Miller and noise effects in a synch..."
...With this unique characteristic, the error path behaves similar to a traditional synchronizer circuit [12]–[14] with the exception of having combinational logic between the sequentials....
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...During metastability, the CLK-to-Q delay push-out exponentially depends on the relationship between the setup time and the input data arrival time [12]–[14]....
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...For DSTB and RFF, the mean time between inducing metastability on PIPELINE ERROR from one EDS circuit in a pipeline stage is calculated as [12]–[14]:...
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...As modeled in (3) and (4), the extra logic between the sequentials exponentially reduces [12]–[14]....
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321 citations
217 citations
Cites background from "Miller and noise effects in a synch..."
...However, the exact nature of synchronization sometimes eludes designers, and as a result synchronization circuits get “optimized” to the point where they do no longer operate correctly....
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...The settling window T (namely the time separation between the two clock inputs to the two flops of the synchronizers) could be a whole clock cycle or a fraction thereof, and could be different for each side, as long as the desired reliability is obtained....
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...The operation of synchronization circuits has been recognized for a long time as being delicate and easy to disturb [1-3, 7-12], but at the same time robust synchronizer design does guarantee safe operation for all practical purposes....
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165 citations
Cites background from "Miller and noise effects in a synch..."
...In the metastable region, the resolution time can be modeled as , where and are device and circuit dependent constants, is the final voltage difference of the latch nodes and is the initial voltage difference from the metastable point [ 6 ]....
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149 citations
References
14,205 citations
110 citations
"Miller and noise effects in a synch..." refers methods in this paper
...This has been demonstrated to be a reasonable first approach for device sizing by Flannagan [1], and again by Kim and Dutton [ 2 ]....
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46 citations
"Miller and noise effects in a synch..." refers methods in this paper
...This has been demonstrated to be a reasonable first approach for device sizing by Flannagan [ 1 ], and again by Kim and Dutton [2]....
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31 citations
"Miller and noise effects in a synch..." refers background or methods in this paper
...Our experience has been that the deterministic line is usually less steep than the slope of the true metastability region [ 3 ]....
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...Using this method insured that any data transition that caused a transition on the output of the DUT occurred within 3 ns of the clock edge [ 3 ]....
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...The second region of interest is from 0 to about 110 ps. We have coined the term “deterministic region” to describe this portion of the curve because the output transition is delayed from a normal propagation but its delay is determined by the setup time [ 3 ]....
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