Minimax design and order estimation of FIR filters for extending the bandwidth of ADCs
Yinan Wang,Håkan Johansson,Hui Xu,Jietao Diao +3 more
- pp 2186-2189
Reads0
Chats0
TLDR
In this paper, the authors derived accurate order estimation formulas for the bandwidth extension filter, which is designed in the minimax sense with the ripple constraints as the design criteria, and demonstrated the performance of the extension filter and its order estimation.Abstract:
The bandwidth of the sampling systems, especially for time-interleaved analog-to-digital converters, needs to be extended along with the rapid increase of the sampling rate. A digitally assisted technique becomes a feasible approach to extend the analog bandwidth, as it is impractical to implement the extension in analog circuits. This paper derives accurate order estimation formulas for the bandwidth extension filter, which is designed in the minimax sense with the ripple constraints as the design criteria. The derived filter order estimation is significant in evaluating the computational complexity from the viewpoint of the top-level system design. Moreover, with the proposed order estimates, one can conveniently obtain the minimal order that satisfies the given ripple constraints, which contributes to reducing the design time. Both the performance of the extension filter and its order estimation are illustrated and demonstrated through simulation examples.read more
Citations
More filters
OtherDOI
Frequency Response Compensation with DSP
TL;DR: This chapter contains sections titled: Filter Table Run-Time Filter Design Calibration Tables FIR Versus IIR Filters Linear Phase FIR Filters Sampling and Signal Frequency Filter Design MATLAB Simulation Implementation in C Extensions Calibation Tables.
Proceedings ArticleDOI
A Pre-Compensation Method for Digital-to-Analog Converter Using Minimax-Designed FIR Filters
TL;DR: This paper derives a FIR filter which is designed in the minimax sense with the ripple constraints as the design criteria for the frequency response compensation of DACs.
Journal ArticleDOI
Analysis, Design, and Order Estimation of Least-Squares FIR Equalizers for Bandwidth Extension of ADCs
TL;DR: This paper considers finite-length impulse-response filters, designed in the least-squares sense, for the bandwidth extension of analog-to-digital converters, which is one of the most important applications in frequency response equalization.
Patent
Bandwidth expansion filter and design method thereof
TL;DR: In this article, the authors proposed a bandwidth expansion filter and a design method for it, which can effectively expand the bandwidth of the TI-ADCs system and enhance the pass band response performance and suppress the stop band noise.
Proceedings ArticleDOI
Reconfigurable FIR Lowpass Equalizers
TL;DR: In this article , a reconfigurable finite-impulse-response (FIR) filter for simultaneous equalization and low-pass filtering is presented, which employs properties of both a variable bandwidth (VBW) filter and a variable equalizer with an adjustable coefficient using the Farrow structure.
References
More filters
Book
Theory and application of digital signal processing
TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Book
Digital Filter Design
Thomas W. Parks,C.S. Burrus +1 more
TL;DR: Introduction to Digital Filters Properties of Finite Impulse-Response Filters Design of Linear-Phase Finite Filters Minimum Phase and Complex Approximation and Comparison of Filtering Alternatives Appendix Index.
Book
Linear and Nonlinear Programming
Stephen G. Nash,Ariela Sofer +1 more
TL;DR: This chapter discusses the development of optimization models for constrained computer programming and some of the methods used to achieve this goal were developed in the 1980s and 1990s.
Journal ArticleDOI
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS
TL;DR: A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency.
Proceedings ArticleDOI
A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS
Kenneth D. Poulton,Robert M. R. Neff,Brian D. Setterberg,Bernd Wuppermann,T. Kopley,R. Jewett,J. Pernillo,C. Tan,A. Montijo +8 more
TL;DR: A 20 GS/s 8-bit ADC achieves a bandwidth of 6 GHz in 0.18 /spl mu/m CMOS and stores data at 20 GB/s into a 1 MB on-chip memory.
Related Papers (5)
Design of multiplier-less continuously variable bandwidth sharp FIR filters using modified harmony search algorithm
James T. George,Elizabeth Elias +1 more