Minimization of Drain-End Leakage of a U-Shaped Gated Tunnel FET for Low Standby Power (LSTP) Application
01 Jan 2021-pp 393-402
Abstract: In this paper, for the first time, the transfer characteristic of a ‘U’-shaped gated tunnel FET (TFET) has been thoroughly investigated considering the real-time adverse effects of gate-to-drain direct tunneling current and gate-induced drain leakage (GIDL) effect using SILVACO ATLAS device simulator. Clearly, these leakage phenomena degrade the device performance, especially for low standby power (LSTP) operation. Hence, for the first time, a novel design modification has been proposed in terms of the optimization of the oxide thickness (TGD) of right vertical arm of the U-shaped gate, in order to mitigate the aforementioned problem. It has been found that when the TGD value is increased to 7 nm from the equivalent oxide thickness (EOT) value of 1.6 nm, the ultimate device becomes optimized in terms of the performance matrices like, IOFF, SSmin, ION/IOFF, etc. Moreover, 43% reduction in delay and almost 11 decades of OFF-state power reduction have been obtained for the optimized device than that of the device having TGD = 1.6 nm, for gate length of 70 nm.
01 Jan 1984-
Abstract: 1. Introduction.- 1.1 The Goal of Modeling.- 1.2 The History of Numerical Device Modeling.- 1.3 References.- 2. Some Fundamental Properties.- 2.1 Poisson's Equation.- 2.2 Continuity Equations.- 2.3 Carrier Transport Equations.- 2.4 Carrier Concentrations.- 2.5 Heat Flow Equation.- 2.6 The Basic Semiconductor Equations.- 2.7 References.- 3. Proeess Modeling.- 3.1 Ion Implantation.- 3.2 Diffusion.- 3.3 Oxidation.- 3.4 References.- 4. The Physical Parameters.- 4.1 Carrier Mobility Modeling.- 4.2 Carrier Generation-Recombination Modeling.- 4.3 Thermal Conductivity Modeling.- 4.4 Thermal Generation Modeling.- 4.5 References.- 5. Analytical Investigations About the Basic Semiconductor Equations.- 5.1 Domain and Boundary Conditions.- 5.2 Dependent Variables.- 5.3 The Existence of Solutions.- 5.4 Uniqueness or Non-Uniqueness of Solutions.- 5.5 Sealing.- 5.6 The Singular Perturbation Approach.- 5.7 Referenees.- 6. The Diseretization of the Basic Semiconductor Equations.- 6.1 Finite Differences.- 6.2 Finite Boxes.- 6.3 Finite Elements.- 6.4 The Transient Problem.- 6.5 Designing a Mesh.- 6.6 Referenees.- 7. The Solution of Systems of Nonlinear Algebraic Equations.- 7.1 Newton's Method and Extensions.- 7.2 Iterative Methods.- 7.3 Referenees.- 8. The Solution of Sparse Systems of Linear Equations.- 8.1 Direct Methods.- 8.2 Ordering Methods.- 8.3 Relaxation Methods.- 8.4 Alternating Direction Methods.- 8.5 Strongly Implicit Methods.- 8.6 Convergence Acceleration of Iterative Methods.- 8.7 Referenees.- 9. A Glimpse on Results.- 9.1 Breakdown Phenomena in MOSFET's.- 9.2 The Rate Effect in Thyristors.- 9.3 Referenees.- Author Index.- Table Index.
17 Nov 2011-Nature
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
23 Jul 2007-IEEE Electron Device Letters
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
01 Dec 2008-
Abstract: The main challenges for Tunnel FETs are experimentally demonstrating SS<60 mV/dec, high ON currents and solving their ambipolar behavior. We have experimentally demonstrated a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS<60 mV/dec. Due to small bandgap of s-Ge and the electrostatics of the DG structure, record high drive current of 300 uA/um (the highest ever reported experimentally for a TFET) and a subthreshold slope of ~50 mV/dec was observed. In addition, to address the ambipolar problem and examine the scalability of TFETs, we have developed a sophisticated TFET simulator that uses a Quantum transport model, Non-local BTBT, complete Bandstructure (real and complex) information, and includes all transitions (direct and phonon assisted). Using this simulator, we have studied the scalability of three asymmetric DG TFET configurations (underlapped drain, lower drain doping and lateral heterostructure) in terms of their ability to solve the ambipolar behavior and achieve high ON and low OFF currents.
01 Feb 2011-IEEE Transactions on Electron Devices
Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.
Related Papers (5)
18 Mar 2009
Mahdi Vadizadeh, Morteza Fathipour
01 Jan 2007
Kathy Boucart, Adrian M. Ionescu
07 May 2019, IEEE Transactions on Electron Devices
Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device
Donghyun Ryu, Ilho Myeong +4 more
14 Mar 2012
Poornendu Chaturvedi, Nitin Goyal
01 Jan 2019, International Journal of Advanced Computer Science and Applications
Sangeeta Mangesh, P. K. Chopra +1 more