Minimizing channel density by shifting blocks and terminals
11 Nov 1991-pp 524-527
TL;DR: The authors present a polynomial time optimal algorithm for solving the problem of minimizing channel density by shifting the blocks that form the sides of the channel and the terminals on the boundary of each block.
Abstract: The authors study the problem of minimizing channel density by shifting the blocks that form the sides of the channel and the terminals on the boundary of each block. Several special cases of this problem have been investigated, but no polynomial time algorithm was known for the general case. The authors present a polynomial time optimal algorithm for solving this problem. For long channels, they propose heuristic approaches to speed up the algorithm. Extensions as well as applications of the algorithm to detailed routing in building-block layout design are also discussed. Preliminary experimental results are very promising. Substantial reductions in routing area were obtained in moderate computation time. >
Citations
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11 Nov 1991
TL;DR: An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition and can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication.
Abstract: An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm. This technique is dependent solely upon the interconnect topology and the direction of signal flows between cells and nets. The formulation of cell gains is extended to model the effect of cell replication, and the necessary modifications to the algorithm are described. >
106 citations
22 Feb 1993
TL;DR: In this approach, the logic is restructured using an intermediate placement solution and then the placement is adjusted to match the new logic structure to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing.
Abstract: In this approach, the logic is restructured using an intermediate placement solution and then the placement is adjusted to match the new logic structure. This ability to change logic structure during layout allows one to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been resynthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared to the original designs. >
23 citations
20 Sep 1993
TL;DR: An O(K/sup 3/L/Sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.
Abstract: Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length. >
16 citations
11 Oct 1992
TL;DR: The present algorithm has important applications in hierarchical layout design of integrated circuits and it is shown that the problem of minimizing wire length by permuting terminals is NP-hard in the strong sense.
Abstract: A linear-time optimal algorithm for minimizing the density of a channel (with exits) by permuting the terminals on the two sides of the channel is presented. It compares favorably with the near-optimal algorithm of J. Cong and K.-Y. Khoo (1991) that runs in superlinear time. The present algorithm has important applications in hierarchical layout design of integrated circuits. In addition, it is shown that the problem of minimizing wire length by permuting terminals is NP-hard in the strong sense. >
6 citations
Cites background from "Minimizing channel density by shift..."
...This type of problems has been studied by many researchers before [3, 4, 5, 8, 11, 13, 14, 15, 16, 17, 18, 20, 23, 24, 25]....
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05 Mar 1993
TL;DR: Algorithms to minimize density for channels with terminals that are movable subject to certain constraints are given and previous results for running time and space are improved.
Abstract: Algorithms to minimize density for channels with terminals that are movable subject to certain constraints are given. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, previous results for running time and space are improved by a factor of L/lg n and L, respectively, where L is the channel length and n is the number of terminals. >
5 citations
References
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01 Jan 1979
42,654 citations
01 Jan 1979
12,336 citations
28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
655 citations
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.
539 citations
28 Jun 1976
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.
Abstract: This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.
364 citations
"Minimizing channel density by shift..." refers background in this paper
...0 If there exists an (:, j, k, U, v)-channel of type 0 (type 1, type '2, type 3. respectively) derivable from the given channel, then w(i, j, k, a, v) (z(i, j, It, U, v), y(i,j, k, a, v). %(a, j, 1, U, v). respectively) is equal to the common local density at column k of all (1, j, 6 , a, v)-channels of type 0 (type 1, type 2, type 3, respectively) derivable from the given channek...
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...The channel routing problem plays an important role in the physical design of VLSI circuits and has been extensively studied in the past [l, 6 , 7, 11, 13, 16, 191....
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...Conventional channel routers assume all terminals (pins) on the two sides of the channel have fixed positions [l, 6 , 7, 11, 191....
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