Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA
TL;DR: This work is making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor and making this ALU portable using MOBILE DDR IO standard in place of default LVCmOS33 IO standard which the authors use in traditional ALU.
Abstract: In this work, we are making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor. It is observed that LVCMOS12 is the most energy efficient than all available LVCMOS having 26.23, 58.37 and 75.65 % less IO power reduction than LVCMOS18, LVCMOS25 and LVCMOS33 respectively at 1 GHz. Then we are making this ALU portable using MOBILE DDR IO standard in place of default LVCMOS33 IO standard which we use in traditional ALU. As we replace LVCMOS with MOBILE DDR, we are achieving 69.07 % portability in terms of IO power and 29.36 % in terms of Leakage power at 2.9 GHz. In next stage, we try to enhance the performance of ALU with MOBILE DDR but not beyond the power consumption with LVCMOS. In that way, we achieve the highest frequency of 12 GHz with MOBILE DDR. That was earlier possible for 3.8 GHz 64-bit ALU using CMOS. In this HDL based implementation of 64-bit ALU on FPGA, Kintex-7 FPGA is used with XC7K70T device and FBG676 package is used.
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TL;DR: A power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA) to reduce the power utilization of UART with the FPGA device in industries.
Abstract: In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.
77 citations
TL;DR: A novel 4-stages energy efficient CTHS approach for Low Power and Thermal Aware Image ALU Design is proposed which is achieving 81.79 % reduction in power consumption which is more than the power reduction by method discussed in Shrivastava et al.
Abstract: Image ALU is a special type of ALU exclusively designed to perform arithmetic and logical operation on Image only. This Image ALU design is able to perform 14 operations. In this work, we have proposed a novel 4-stages energy efficient CTHS (C-Capacitance Scaling, T-Thermal Scaling, H-HSTL I/O Standard, S-SSTL I/O Standard) approach for Low Power and Thermal Aware Image ALU Design. CTHS technique is achieving 81.79 % reduction in power consumption which is more than the power reduction by method discussed in Shrivastava et al. (IEEE Trans Very Large Scale Integr Syst 18(6):988---997, 2010); Yoonjin and Mahapatra (IEEE Trans Very Large Scale Integr Syst 18(1):15---28, 2010); Chatterjee and Sachdev (IEEE Trans Very Large Scale Integr Syst 13(11):1296---1304, 2005); Wijeratne et al. (IEEE J Solid State Circuits 42(1):26---37, 2007); Nehru et al. (International conference on advances in engineering, science and management pp 145---149, 2012); Ho et al. (IEEE international symposium on circuits and systems pp 353---356, 2013); Rani et al. (3rd in international conference on electronics computer technology pp 224---228, 2011) for ALU. There is 38.63 % reduction in I/O Power and 46.42 % reduction in leakage power, when we scale down capacitance from 50 to 5 pF on 28 nm technology based Kintex-7 FPGA on 100 GHz device operating frequency. FPGA is a Filed Programmable Gate Array. There is 67.05 % reduction in I/O Power when we scale down ambient temperature from 50 to 10 °C on 100 GHz frequency. There are 5 different climates in koppen climate classification. We are taking 5 different values in order to nearly represent 5 climates. Using high profile Heat Sink and 500 LFM Airflow, there is 75.39 % leakage power reduction from the last optimized result of capacitance scaling and 85.84 % leakage power reduction from the initial power dissipation. On 3rd stage, using HSTL I/O Standard, there is 64.53 % power reduction from the initial power dissipation. There is 41.06, 59.26, 78.75 % power reduction from HSTL_II_DCI_18 to HSTL_I_12 on 100, 10 and 1 GHz. On 4th and final stage, using SSTL I/O Standard, there is 81.79 % power reduction from the initial power dissipation. There is 61.83 % reduction in junction temperature, when we apply 500 LFM airflow and high profile heat sink in compare to 250 LFM airflow and no heat sink. LFM is an acronym for Linear Feet per Minute. LFM is a unit of airflow that help us to control junction temperature of FPGA. Unit of leakage power is Watt (W) and Junction Temperature is degree Celsius (°C).
41 citations
TL;DR: This work has designed IoTs enable power efficient and thermal aware frame buffer to store the frames and uses that frame to detect changes in object position and embedding a 128-bit IPv6 address into frame buffer.
Abstract: Object tracking based on active contour modeling is an image processing related technology that uses snapshots of the object under consideration to track it via robot in the real world. Nowadays, the word is moving towards the internet of things (IoTs) and having significant effect on our daily life. In this work, we have designed IoTs enable power efficient and thermal aware frame buffer to store the frames and uses that frame to detect changes in object position. In order to make IoTs enable design, we are embedding a 128-bit IPv6 address into frame buffer. In order to test the compatibility of this design with wireless network, we are operating this design with different operating frequency of WLAN channel. The operating frequency of WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, 802.11p and 802.11d are 900 MHz, 2.4, 3.6, 5, 5.9 and 60 GHz respectively. There is no change in signal power, clock power, IO power, when we scale down ambient temperature from 70 to 30 °C. There are 98---89 % saving in signal power, 2---85 % reduction in clock power, 90---99 % saving in IO power with WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, 802.11p in compare to power dissipation with 802.11ad. There is 71.11, 72.60, 73.96, 74.28, and 74.42 % reduction in leakage power with WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, and 802.11p, when we scale down ambient temperature from 70 to 30 °C. IoTs enable frame buffer design can be controlled from any part of this globe. Another design characteristic of this frame buffer is that it is 3-D frame buffer which gives us an added advantage over 2-D frame buffer that store image only in X, Y orientation. Capability to analyze third dimension helps us to track object more efficiently.
35 citations
TL;DR: This work designs an FIR filter that will energy efficient as well as faster than traditional design and finds the most energy efficient architecture and also finds the architecture that will deliver highest performance among these four architectures taken under consideration.
Abstract: There are many areas of communication and network, which have open scope to use FIR filter. Therefore, energy efficient FIR filter will increase lifetime of network and FIR filter with less delay and latency will increase performance of network. In this work, we are going to design an FIR filter that will energy efficient as well as faster than traditional design. Three different FPGA and SOC are taken under consideration and our design is implemented on these four ICs and we find the most energy efficient architecture and also find the architecture that will deliver highest performance among these four architectures taken under consideration. There is 47.74% reduction in latency when we migrate our FIR Filter design from 28 nm process technology based seven series architecture to 20 nm process technology based ultrascale architecture. When we analyze power dissipation of Artix-7, Kintex-7, Zynq and Ultrascale FPGA then we conclude that Zynq 7000 All programmable SOC is power hungry architecture and Kintex ultrascale architecture is the most energy efficient architecture that dissipates 20.86% less power than Zynq 700 All programmable SOC. For performance evaluation, we have taken benchmark C code of FIR provide by Xilinx. We transform that C code into HDL using Vivado HLS 2016.2 before power analysis on Vivado 2016.2. Ultrascale FPGA is generally used for packet processing in 100G networking and heterogeneous wireless infrastructure.
26 citations
14 Nov 2014
TL;DR: This work is integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA with mechanism of ambient (room) temperature scaling and energy efficient LVCMOS I/O standard.
Abstract: In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. Nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking pattern is changing with evolution of mankind? This paper deals with that question and the whole work is going in direction to get solution of this problem with mechanism of ambient (room) temperature scaling and energy efficient LVCMOS I/O standard. LVCMOS is an acronym for low voltage complementary metal oxide semiconductor. In this Vedic multiplier, we are using three LVCMOS I/O standard. LVCMOS12 is available only in 65nm and 40nm FPGA. Rest LVCMOS18 and LVCMOS25 is available among 40nm, 65nm and 90nm FPGA. In order to test the thermal sustainability of our Vedic multiplier, we are testing it in three different room temperature 20°C, 30°C, and 40°C. Using LVCMOS25, there is 12.99%, 19.23% and 10.28% reduction in power dissipation on 90nm, 65nm and 40nm respectively. For LVCMOS25, when our Vedic multiplier design is migrated from 40nm design to 90nm design, there is 87.72% reduction in power dissipation of Vedic multiplier when temperature is constant 20°C.
21 citations
References
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Book•
23 Jul 2010TL;DR: This book explores power optimization opportunities and their exploitation at various levels of abstraction and concludes in a case study illustrating the application of the major techniques to a graphics processor.
Abstract: This book addresses power optimization in modern electronic and computer systems. Several forces aligned in the past decade to drive contemporary computing in the direction of low power and energy-awareness: the mobile revolution took the world by storm; power budgets forced mainstream processor designers to abandon the quest for higher clock frequency; and large data centers with overwhelming power costs began to play vital roles in our daily lives. Power optimization was elevated to a first class design concern, forcing everyone from the process engineer, circuit designer, processor architect, software developer, system builder, and even data center maintainer to make conscious efforts to reduce power consumption using myriad techniques and tools. This book explores power optimization opportunities and their exploitation at various levels of abstraction. Fundamental power optimizations are covered at each level of abstraction, concluding in a case study illustrating the application of the major techniques to a graphics processor. This book covers a comprehensive range of disparate power optimizations and is designed to be accessible to students, researchers, and practitioners alike.
71 citations
"Mobile DDR IO Standard Based High P..." refers background in this paper
...Power optimization is gaining importance as first design concern, forcing EDA Personnel either process engineer or circuit designer or processor architect or software engineer or system builder or data center maintainer to make energy efficient efforts using different optimal energy efficient techniques and tools [2]....
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...Power reduction possibilities and their usage in different levels of abstraction is discussed in [2]....
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01 Nov 2007
TL;DR: 512 Mb Mobile SDRAM with on-chip error-correction code (ECC), which supports either single or double data rate and operates on a 1.8 V power supply, is developed and could be 106 times higher by the ECC than that of the conventional DRAM.
Abstract: 512 Mb Mobile SDRAM with on-chip error-correction code (ECC), which supports either single or double data rate and operates on a 18 V power supply, is developed The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty The ratio of ECC area increase compared with the conventional mobile DRAM is 15%, and the fast comparing circuits of built-in Hamming code technique check 12 cell data simultaneously and satisfy the specification of 400Mbps DDR SDRAM The self refresh period at standby state shows about 6 times increase reducing the self refresh current to be less than 100uA at 85degC The newly adopted DCCS in the ECC, which is resistant from the clustered failures, and the concurrent row redundancy produce a synergistic fault-tolerance effect The reliability could be 106 times higher by the ECC than that of the conventional DRAM
40 citations
10 Apr 2013
TL;DR: There is 67.04% dynamic power reduction with LVCMOS12 when the authors migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6FPGA, and there is 81.19%, 92.05% and 73.41% dynamicPower reduction in ALU with LVDCI IO standard in place of LVD CI_DV2, HSTL_I, and LVCmOS12 respectively.
Abstract: There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power reduction when using LVCMOS12 in place of HSTL_II_18 and SSTL2_I_DCI respectively. We achieved 65.56%, 72.59% and 73.41% dynamic power reduction in ALU with LVDCI IO standard in place of LVDCI_DV2, HSTL_I, and LVCMOS12 respectively. There is 68.34% and 52.51% dynamic power reduction in ALU when using LVCMOS12 and LVCMOS15 in place of LVCMOS25. There is 62.45% dynamic power reduction in ALU, when we use HSTL_I in place of SSTL2_I_DCI. Power is directly proportional to frequency. With increase in frequency, there is increase in power consumption irrespective of IO standard. LVCMOS is the only IO standard, which takes less power when we upgrade our design to latest FPGA.
37 citations
"Mobile DDR IO Standard Based High P..." refers methods in this paper
...In the second stage, we reduce power dissipation by changing the IO standard from LVCMOS33 to LVCMOS25, LVCMOS18, and LVCMOS15 respectively, which is described in Sect....
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...51 % IO power reduces in 8-bit ALU when using LVCMOS12 and LVCMOS15 in place of LVCMOS25 [8]....
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...To make it energy efficient, we have applied four different LVCMOS IO standards in 64-bit ALU and found that out of four, LVCMOS15 is the most energy efficient where IO Power reduces to 26.03, 58.37 and 75.65 % as compared to LVCMOS18, LVCMOS25 and LVCMOS33 respectively at 2.9 GHz....
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...LVCMOS33 is an default IO standard which works on 3.3 V. the other variant of LVCMOS, which are LVCMOS25, LVCMOS18 and LVCMOS15 work on 2.5, 1.8 and 1.5 V, respectively....
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...68.34 and 52.51 % IO power reduces in 8-bit ALU when using LVCMOS12 and LVCMOS15 in place of LVCMOS25 [8]....
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TL;DR: This paper presents a specific, fully-automated and portable design methodology used to optimize implementations of AC-DC rectifiers using MOS diodes, and theoretically analyzed Output voltage and efficiency are theoretically analyzed taking into account influences of devices DC and AC characteristics, input signal voltages and frequencies as well as load currents, temperatures, backgate voltages, capacitors and diode parasitic capacitances.
Abstract: This paper presents a specific, fully-automated and portable design methodology used to optimize implementations of AC-DC rectifiers using MOS diodes. Output voltage and efficiency are theoretically analyzed taking into account influences of devices DC and AC characteristics, input signal voltages and frequencies as well as load currents, temperatures, backgate voltages and even capacitors and diodes parasitic capacitances. An experimental voltage multiplier is designed in a 1 μm multiple-threshold voltage SOI CMOS technology for ultra low power applications at 13.56 MHz .
21 citations
"Mobile DDR IO Standard Based High P..." refers methods in this paper
...In our work, we are making low power ALU design to achieve portability [6]....
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...Methodology of automated design is used to optimize design and implementations of AC-DC rectifiers using MOS diodes to make it portable [6]....
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01 Jan 2008
TL;DR: In this paper, the power savings that can be expected, the power-delay trade-offs, and the implications of adaptive voltage scaling (AVS) and adaptive body biasing (ABB) on present semiconductor technologies are discussed.
Abstract: In this chapter, we concentrate on technological quantitative pointers for adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in modern CMOS digital designs. In particular, we will present the power savings that can be expected, the power-delay trade-offs that can be made, and the implications of these techniques on present semiconductor technologies. Furthermore, we will show to which extent process-dependent performance compensation can be used. Our presentation is a result of extensive analyses based on test-circuits fabricated in the state-of-the-art CMOS processes. Experimental results have been obtained for both 90nm and 65nm CMOS technology nodes.
15 citations