Mobility engineering and a metal–insulator transition in monolayer MoS 2
Summary (2 min read)
S1. Device fabrication
- Si wafers covered with 270 nm thermally grown SiO 2 serve as the substrate and back-gate for the MoS 2 devices.
- Single and few-layer MoS 2 flakes are obtained by standard micromechanical cleavage technique.
- In the inset of Figure 1a the authors present an optical image of the device after standard lift-off procedure performed in acetone.
- In order to remove resist residue and decrease contact resistance in their devices, the authors perform annealing at 200 ºC in Ar atmosphere for 2 hours.
- The top-gate electrode is made by depositing Cr/Au (10/50 nm) layer by electron-beam evaporation and liftoff in acetone.
S2. Device details
- The authors have performed measurements on two devices in single-gate configuration, two devices in single-gate configuration covered with a 30 nm thick HfO 2 layer and six devices in dual-gate configuration.
- Their characteristics are summarized in the following table: W is the channel width and L 12 is the distance between voltage probes used in four-contact measurements.
- K F ·l e is the Ioffe-Regel parameter related to the metal-insulator transition point and n MIT is the electron concentration at which the transition occurs, extracted from Hall-effect measurements.
S4. Schottky barrier height in a single-gate device
- From the temperature dependence of conductance for different gate voltages (Figure 2b in the main text) the authors were able to extract activation energy E a dependence on gate voltage V bg , Figure S2 .
- From the deviation of the E a from the linear trend, occurring when barrier tunneling becomes the dominant mechanism for charge carrier injection, the authors estimate a Schottky barrier height Φ SB ∼ 45meV.
- This value is relatively small and does not have a significant influence on their mobility extraction from four-contact measurements.
S5. Hysteresis in G -V tg curves
- Double sweeps of conductance G as a function of the top gate voltage V tg at several temperatures for the double-gated device presented in the manuscript are shown in S3 demonstrating no hysteresis for all temperatures.
- This excludes the possibility of device hysteresis being behind the observation of the metal-insulator transition.
S6. Capacitance determination
- The authors extract device capacitance from Hall effect measurements and the transverse Hall resistance R xy for all MoS 2 devices covered with a dielectric layer in order to accurately determine the mobility.
- From the inverse slope of R xy vs magnetic field (an example is shown on figure 5a in the main manuscript), the authors can directly determine the electron density n 2D in the MoS 2 channel.
- In Figure S4a , the authors show the dependence of the charge density on the back-gate voltage for a device in which the MoS 2 channel is covered with a 20nm thick HfO 2 layer.
- From the slope, the authors can extract the correct capacitance of the back-gate, C bg-Hall , which in this case is 2.4 times higher than the capacitance calculated using the parallel-plate capacitance model geom 0 ox,bottom / r C d = ε ε .
- This shows that using the parallel-plate capacitance model in place of an actual, measured capacitance in this type of situations can result in underestimating the strength of the capacitive coupling and field-induced charge density and lead to an overestimated mobility.
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Frequently Asked Questions (12)
Q2. What is the simplest way to write ea?
Assuming that activated behavior arises from activation of electrons from the Fermi energy EF to conduction band edge Ec, the authors can write Ea = Ec-EF.
Q3. What is the name of the paper?
The source, drain and voltage probes were defined by electron-beam lithography followed by deposition of 90 nm thick Au electrodes.
Q4. What is the hysteresis of the device?
The authors extract device capacitance from Hall effect measurements and the transverse Hall resistance Rxy for all MoS2 devices covered with a dielectric layer in order to accurately determine the mobility.
Q5. How high is the Ea of the top-gated device?
From the deviation of the Ea from the linear trend, occurring when barrier tunneling becomes the dominant mechanism for charge carrier injection, the authors estimate a Schottky barrier height ΦSB ∼ 45meV.
Q6. How does the hysteresis of conductance G affect the MIT?
From the deviation of the Ea from the linear trend, occurring when barrier tunneling becomes the dominant mechanism for charge carrier injection, the authors estimate a Schottky barrier height for the charge carrier injection from gold electrodes into monolayer MoS2 of ΦSB∼ 45 meV.S5.
Q7. What is the charge density of the back gate?
El ectro nco ncen tratio nn (101 3cm -2)1098765Back gate voltage Vbg (V)Cbg-Hall = 6.88 · 10 -7 F/cm2 Cbg-geometric = 0.13 · 10 -7 F/cm2Cbg-Hall / Cbg-geometric = 531.11.00.90.80.7El ectro nco ncen tratio nn (101 3 cm -2)8075706560Back gate voltage Vbg (V)Cbg-Hall = 3.4 · 10 -8 F/cm-2 Cbg-geometric = 1..26 · 10 -8 F/C·cm-2Cbg-Hall / Cbg-geometric = 2.4NATURE MATERIALS | www.nature.com/naturematerials
Q8. How was the transport of the devices performed?
All devices are wirebonded onto chip carriers and transferred to a cryostat where the transport measurements were performed in vacuum from room temperature down to 300 mK.
Q9. How much is the charge density increased by the parallel-plate capacitance?
The capacitance is increased by a factor of 53 with respect to the parallel-plate capacitance where one plate is the back-gate and the other the MoS2 channel.a b 3.02.52.01.51.0
Q10. What is the inverse slope of Rxy vs magnetic field?
From the inverse slope of Rxy vs magnetic field (an example is shown on figure 5a in the main manuscript), the authors can directly determine the electron density n2D in the MoS2 channel.
Q11. What is the hysteresis of the conductance G curve?
The variation of the electron density extracted from Rxy as a function of the control-gate voltage for two typical situations encountered in the literature is shown in Figure S4.
Q12. How many nts are in the eff?
From the slope of the curve (main text, solid black line in Figure 4b) related to monolayer device in Figure 4b at lower gate voltages when the device is fully depleted, that corresponds to a bandwidth of 44 meV, the authors estimate the concentration of depleted charges to be nt ~ 6.3 · 1011 cm-2.