Modeling of Advanced RF Bulk FinFETs
11 Apr 2018-IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers Inc.)-Vol. 39, Iss: 6, pp 791-794
TL;DR: In this article, the Berkeley short-channel IGFET model-common multi-gate model is improved to account for the impact of substrate coupling on the RF parameters, and the model demonstrates excellent agreement with the measured data over a broad range of frequencies.
Abstract: The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.
Citations
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01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0
207 citations
TL;DR: In this article, the effects of stack spacing and number of stacks on device performance were studied and a substack design for improved RF performance was proposed, which can improve cut-off frequency by approximately 10% and minimum number of substacks and minimum substack spacing should be used.
Abstract: Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency ( ${F}_{{t}}$ ) by ~10% and minimum number of substacks and minimum substack spacing should be used.
24 citations
Cites methods from "Modeling of Advanced RF Bulk FinFET..."
...FinFET has been used successfully from 22- to 7-nm node [2]–[5]....
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TL;DR: In this paper, the authors investigate the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series.
Abstract: This paper investigates the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series. Linearity sweet spots with respect to gate voltage and RF power, as well as its drain voltage dependence, are examined. Key BSIM-CMG model parameters required for simultaneous fitting of dc I–V , S-parameters, and intermodulation distortion are identified and demonstrated. Volterra series analysis shows that distortion resulting from ${V}_{\textsf {DS}}$ derivatives of ${I}_{\textsf {DS}}$ dominates at most biases. A minimum third-order intercept gate voltage ${V}_{\textsf {GS,IP3}}$ of 0.5 V is observed, compared with 0.7 V in a 28-nm high- ${k}$ metal-gate planar device.
11 citations
Cites methods from "Modeling of Advanced RF Bulk FinFET..."
...CMG [14], following the step-by-step extraction strategy of [15] using dc and S-parameter data....
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TL;DR: In this paper, the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level is analyzed.
Abstract: In this work, we analyze the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level. The 3-D thermal TCAD simulations, after careful calibration with measurements, are performed to analyze the impact of SHE in a broad range of frequency. Furthermore, we use the TCAD calibrated BSIM-CMG model to analyze the impact of SHE in NC-FinFET at the circuit level, after including a physics-based model to capture the NC effect. For the first time, we analyze the impact of a nonuniform distribution of temperature dissipated from the channel region to gate-stack in NC-FinFETs. On account of the thermal insulating properties of the gate-stack, the ferroelectric (FE) layer is found to be cooler than the channel region under the impact of SHE. We demonstrate that neglecting that and, hence, using the channel temperature to evaluate the temperature-dependent parameter $\alpha $ (in the Landau–Khalatanikov model of NC effect) of the FE layer result in a significant overestimation of SHE-induced degradations, such as in the NC voltage gain. Based on our TCAD analysis, we propose a relation between gate-stack temperature and the channel temperature and use this to accurately model the $\alpha $ parameter and, hence, SHE in NC-FinFETs. The SHE is found to dominate for both FinFET and NC-FinFET in the gigahertz range, which eventually degrades the performance at the circuit level, which is further confirmed using ring oscillator (RO) simulations.
11 citations
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
Abstract: In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance ( ${g}_{{\text {ds}}}$ ) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ( $\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data.
11 citations
References
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Journal Article•
TL;DR: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: 53 ■ IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 2005 THE DESIGN OF CMOS RADIOFREQUENCY INTEGRATED CIRCUITS, 2ND ED By Thomas Lee, Cambridge University Press, 2003. All-CMOS radio transceivers and system-on-a-chip are rapidly making inroads into a wireless market that, for years, was dominated by bipolar solutions. On wireless LAN and Bluethooth, RF CMOS is especially dominant, and it is becoming also in GSM cellular and GPS receivers. Hence, books that cover this widespread domain respond to a real need. The first edition of this book, published on 1998, was a pioneering textbook on the field of RF CMOS design. This second edition is a very interesting and upgraded version that includes new material and revised topics. In particular, it now includes a chapter on the fundamentals of wireless systems. The chapter on IC components is greatly expanded and now follows that on passive RLC components. The chapter on MOS devices has been updated since it includes the understanding of the model for the shorth-channel MOS and considers and discusses the scaling trends and its impact on the next several years. It has also expanded the topic of power amplifiers; indeed, it now also covers techniques for linearization and efficiency enhancement. Low-noise amplifiers, oscillators, and phase noise are now expanded and treated with more detail. Moreover, the chapter on transceiver architectures now includes much more detail, especially on direct-conversion architecture. Finally, additional commentary on practical details on simulations, floorplanning, and packaging has been added. The first edition of this book widely covered all the main arguments needed in the CMOS design context and provided a bridge between system and circuit issues. This second edition, which is upgraded and improved, is really useful, both in the industry and academia, for the new generation of RF engineers. Indeed, it is suited for students taking courses on RF design and is a valuable reference for practicing engineers. Of course, the arguments treated in the textbook lead up to low-frequency analog design IC topics. Hence, readers have to be intimately familiar with that subject. The book is divided into 20 chapters: 1) A Nonlinear History of Radio 2) Overview of Wireless Principles 3) Passive RLC Networks 4) Characteristics of Passive IC Components 5) A Review of MOS Device Physics; 6) Distributed Systems 7) The Smith Chart and S-Parameters 8) Bandwidth Estimation Techniques 9) High-Frequency Amplifier Design 10) Voltage References and Biasing 11) Noise 12) LNA Design 13) Mixers 14) Feedback Amplifiers 15) RF Power Amplifiers 16) Phase Locked Loop 17) Oscillators and Synthesizers 18) Phase Noise 19) Architectures 20) RF Circuits Through the Ages. Moreover, it contains over 100 circuit diagrams and many homework problems. Gaetano Palumbo
3,949 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
...Model gives the correct slope of n for the nth harmonic component [25]....
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Book•
01 Jan 2006
TL;DR: In this article, the authors present a short history of the EKV most model and its application in IC design, and present an extended version of the model with an extended charge-based model.
Abstract: Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.
307 citations
"Modeling of Advanced RF Bulk FinFET..." refers background or methods in this paper
...The transit frequency (cutoff frequency) ft is extracted by extrapolating the |H21| characteristic to 0 dB [21]....
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...Another important FOM, that accounts for the gate resistance Rg and the drainto-bulk capacitance Cgd , is the unilateral power gain U [21]....
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TL;DR: In this paper, a charge-based model of the intrinsic part of the MOS transistor is presented, which is based on the forward and reverse charges q/sub f/ defined as the mobile charge densities, evaluated at the source and at the drain.
Abstract: This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic elements. A complete charge-based model of the intrinsic part is presented. The main advantage of this new charge-based model is to provide a simple and coherent description of the DC, AC, nonquasi-static (NQS), and noise behavior of the intrinsic MOS that is valid in all regions of operation. It is based on the forward and reverse charges q/sub f/ and q/sub r/ defined as the mobile charge densities, evaluated at the source and at the drain. This intrinsic model also includes a new simplified NQS model that uses a bias and frequency normalization allowing one to describe the high-order frequency behavior with only two simple functions. The extrinsic model includes all the terminal access series resistances, and particularly the gate resistance, the overlap, and junction capacitances as well as a substrate network. The latter is required to account for the signal coupling occurring at RF from the drain to the source and the bulk, through the junction capacitances. The noise model is then presented, including the effect of the substrate resistances on the RF noise parameters. All the aspects of the model are validated for a 0.25-/spl mu/m CMOS process.
194 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
...(c) Simple equivalent circuit of the substrate components for the device in the off-state [7], [8]....
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01 Dec 1998
TL;DR: In this paper, a physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices.
Abstract: A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices. The accuracy of the model is validated with 2D simulations and experimental data. In addition, the effect of the gate resistance on the device noise behavior has been studied with measured data. The result shows that an accurate gate resistance model is essential for the noise modeling.
171 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
..., virtual gate induced channel resistance Rgch) seen from the gate [20]....
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...At low frequencies, both gate resistance components contribute to the input resistance (real H11) [20], whereas at high frequencies, Rgch is bypassed by overlap and fringing capacitances, and the effective input resistance becomes Rgeltd + (Rsub||Rs ||Rd) as shown in Figure 3(c)....
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TL;DR: A new MOSFET model is presented that overcomes the errors present in state-of-the-art models and comparison with measured data is presented to validate the new model.
Abstract: Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model.
138 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
...The Gummel symmetry test verifies the symmetry and continuity of the drain current and its higher order derivatives around Vds = 0V [23]....
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