Modeling of Advanced RF Bulk FinFETs
11 Apr 2018-IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers Inc.)-Vol. 39, Iss: 6, pp 791-794
TL;DR: In this article, the Berkeley short-channel IGFET model-common multi-gate model is improved to account for the impact of substrate coupling on the RF parameters, and the model demonstrates excellent agreement with the measured data over a broad range of frequencies.
Abstract: The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.
Citations
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01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0
207 citations
TL;DR: In this article, the effects of stack spacing and number of stacks on device performance were studied and a substack design for improved RF performance was proposed, which can improve cut-off frequency by approximately 10% and minimum number of substacks and minimum substack spacing should be used.
Abstract: Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency ( ${F}_{{t}}$ ) by ~10% and minimum number of substacks and minimum substack spacing should be used.
24 citations
Cites methods from "Modeling of Advanced RF Bulk FinFET..."
...FinFET has been used successfully from 22- to 7-nm node [2]–[5]....
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TL;DR: In this paper, the authors investigate the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series.
Abstract: This paper investigates the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series. Linearity sweet spots with respect to gate voltage and RF power, as well as its drain voltage dependence, are examined. Key BSIM-CMG model parameters required for simultaneous fitting of dc I–V , S-parameters, and intermodulation distortion are identified and demonstrated. Volterra series analysis shows that distortion resulting from ${V}_{\textsf {DS}}$ derivatives of ${I}_{\textsf {DS}}$ dominates at most biases. A minimum third-order intercept gate voltage ${V}_{\textsf {GS,IP3}}$ of 0.5 V is observed, compared with 0.7 V in a 28-nm high- ${k}$ metal-gate planar device.
11 citations
Cites methods from "Modeling of Advanced RF Bulk FinFET..."
...CMG [14], following the step-by-step extraction strategy of [15] using dc and S-parameter data....
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TL;DR: In this paper, the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level is analyzed.
Abstract: In this work, we analyze the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level. The 3-D thermal TCAD simulations, after careful calibration with measurements, are performed to analyze the impact of SHE in a broad range of frequency. Furthermore, we use the TCAD calibrated BSIM-CMG model to analyze the impact of SHE in NC-FinFET at the circuit level, after including a physics-based model to capture the NC effect. For the first time, we analyze the impact of a nonuniform distribution of temperature dissipated from the channel region to gate-stack in NC-FinFETs. On account of the thermal insulating properties of the gate-stack, the ferroelectric (FE) layer is found to be cooler than the channel region under the impact of SHE. We demonstrate that neglecting that and, hence, using the channel temperature to evaluate the temperature-dependent parameter $\alpha $ (in the Landau–Khalatanikov model of NC effect) of the FE layer result in a significant overestimation of SHE-induced degradations, such as in the NC voltage gain. Based on our TCAD analysis, we propose a relation between gate-stack temperature and the channel temperature and use this to accurately model the $\alpha $ parameter and, hence, SHE in NC-FinFETs. The SHE is found to dominate for both FinFET and NC-FinFET in the gigahertz range, which eventually degrades the performance at the circuit level, which is further confirmed using ring oscillator (RO) simulations.
11 citations
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
Abstract: In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance ( ${g}_{{\text {ds}}}$ ) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ( $\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data.
11 citations
References
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TL;DR: In this paper, the authors present dc and ac tests that verify whether a MOSFET model is symmetric with respect to a source-drain reversal, and also verify the symmetry of gate and bulk currents.
Abstract: This paper presents dc and ac tests that verify whether a MOSFET model is symmetric with respect to a source-drain reversal. The tests are valid in the presence of and also verify the symmetry of gate and bulk currents, and evaluate the symmetry of all components of MOSFET charge models
94 citations
TL;DR: In this paper, the authors characterized the dynamic self-heating effect in n-channel SOI FinFETs, and the dependence of thermal resistance on finFET geometry is discussed.
Abstract: Multigate semiconductor devices are celebrated for improved electrostatic control and reduced short-channel effects. However, nonplanar architectures suffer from increases of access resistances and capacitances, as well as self-heating effects due to confinement and increased phonon boundary scattering. In silicon-on-insulator (SOI) technology, the self-heating effects are aggravated by the presence of a thick buried oxide with low thermal conductivity, which prevents effective heat removal from the device active region to the Si substrate. Due to the shrinking of device dimensions in the nanometer scale, the thermal time constant that characterizes the dynamic self-heating is significantly reduced, and radio frequency extraction techniques are needed. The dynamic self-heating effect is characterized in n-channel SOI FinFETs, and the dependence of thermal resistance on FinFET geometry is discussed. It is experimentally confirmed that the fin width and the number of parallel fins are the most important parameters for thermal management in FinFETs, whereas fin spacing plays a less significant role.
81 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
...as channel heat dissipates easily in bulk FinFETs [9] compared to FDSOI [10]–[14] or SOI FinFETs [15], [16]....
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...However, this difference is very small in bulk FinFETs, as channel heat dissipates easily in bulk FinFETs [9] compared to FDSOI [10]–[14] or SOI FinFETs [15], [16]....
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...[19] A. J. Scholten, G. D. J. Smit, R. M. T. Pijper, L. F. Tiemeijer, H. P. Tuinhout, J.-L. P. J. van der Steen, A. Mercha, M. Braccioli, and D. B. M. Klaassen, “Experimental assessment of self-heating in SOI FinFETs,” in IEDM Tech....
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01 Jan 2015
TL;DR: FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Venugopalan, Sourabh Khandelwal, Juan Pablo Duarte, Navid Paydavosi, Ai Niknejad, Chenming Hu.
Abstract: ABOUT THE AUTHORS Yogesh Singh Chauhan Assistant Professor, Department of Electrical Engineering, Indian Institute of Technology (IIT) Kanpur, India Darsen Lu Research Scientist, IBM Research. Sriramkumar Venugopalan Samsung Electronics Sourabh Khandelwal University of California, Berkeley, USA Juan Pablo Duarte University of California, Berkeley, USA Navid Paydavosi Device Engineer, Intel Corp., Oregon, USA Ai Niknejad Professor in the EECS department at UC Berkeley, USA. Chenming Hu Professor Emeritus at University of California at Berkeley, CA, FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Venugopalan, Sourabh Khandelwal, Juan Pablo Duarte, Navid Paydavosi, Ai Niknejad Chenming Hu
80 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
...Hence, the DC compact model alone is not sufficient to accurately predict the device behavior over a wide frequency range [5]....
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22 Nov 2004
TL;DR: It is found that non-singular behavior at zero drain bias is essential for qualitatively correct simulations of the third harmonic power dependence in MOSFET simulations.
Abstract: This paper examines the relation between the structure of a compact MOSFET model and its ability to model harmonic distortion. It is found that non-singular behavior at zero drain bias is essential for qualitatively correct simulations of the third harmonic power dependence. Specifically, nonlinear distortion analysis requires that the Gummel symmetry condition be satisfied by the compact model. A simple procedure to enforce the Gummel symmetry without increasing the complexity of the model is incorporated in an advanced surface-potential-based MOSFET model to enable correct harmonic distortion modeling.
65 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
...The symmetry and continuity of the derivatives help the model in passing the harmonic-balance (HB) test [24]....
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TL;DR: In this article, the high frequency (HF) behavior of substrate components in MOSFETs is studied at different bias conditions for a 0.35 /spl mu/m BICMOS technology in the frequency range up to 10 GHz.
Abstract: The high-frequency (HF) behavior of substrate components in MOSFETs is studied at different bias conditions for a 0.35 /spl mu/m BICMOS technology in the frequency range up to 10 GHz. It was found that the observed strong bias dependence of the real part of admittance y/sub 22/, Re{y/sub 22/}, is mainly contributed by the channel conductance. A very weak bias dependence of substrate resistance was found after deembedding the measured y/sub 22/ to remove the influence of channel resistance R/sub ds/ and gate-to-drain capacitance C/sub gd/. The results are key to the understanding and modeling of the HF behavior of MOSFET substrate components for RF IC design.
61 citations