Journal ArticleDOI
Modeling of Advanced RF Bulk FinFETs
Pragya Kushwaha,Harshit Agarwal,Yen-Kai Lin,Ming-Yen Kao,Juan Pablo Duarte,Huan-Lin Chang,W. Wong,J. Fan,Xiayu,Yogesh Singh Chauhan,Sayeef Salahuddin,Chenming Hu +11 more
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TLDR
In this article, the Berkeley short-channel IGFET model-common multi-gate model is improved to account for the impact of substrate coupling on the RF parameters, and the model demonstrates excellent agreement with the measured data over a broad range of frequencies.Abstract:
The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.read more
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Book ChapterDOI
The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Journal ArticleDOI
Design Optimization Techniques in Nanosheet Transistor for RF Applications
TL;DR: In this article, the effects of stack spacing and number of stacks on device performance were studied and a substack design for improved RF performance was proposed, which can improve cut-off frequency by approximately 10% and minimum number of substacks and minimum substack spacing should be used.
Journal ArticleDOI
Intermodulation Linearity Characteristics of 14-nm RF FinFETs
TL;DR: In this paper, the authors investigate the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series.
Journal ArticleDOI
Impact of Self-Heating on Negative-Capacitance FinFET: Device-Circuit Interaction
TL;DR: In this paper, the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level is analyzed.
Journal ArticleDOI
Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
References
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Journal ArticleDOI
RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model
TL;DR: In this article, the performance of the BSIM-IMG model for fully depleted silicon-on-insulator (FDSOI) transistors is discussed with experimental data.
Proceedings ArticleDOI
14nm FinFET technology for analog and RF applications
Jagar Singh,AJ Bousquet,Jerome Ciavatti,Kumaran Sundaram,Jen Shuang Wong,Kok Wai Johnny Chew,Abhijit Bandyopadhyay,Shuming Li,Abdellatif Bellaouar,Shesh Mani Pandey,Baofu Zhu,Alexander L. Martin,C. Kyono,Jung-Suk Goo,H. S. Yang,A. Mehta,X. Zhang,Owen Hu,S. Mahajan,E. Geiss,S. Yamaguchi,S. B. Mittal,Ram Asra,Palanivel Balasubramaniam,Josef S. Watts,David Harame,Ravi M. Todi,Srikanth Samavedam,D. K. Sohn +28 more
TL;DR: In this paper, a 14nm analog and RF technology based on a logic FinFET platform for the first time was highlighted, and an optimized RF device layout showed excellent F t /F max of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively.
Book ChapterDOI
Bulk FinFETs: Design at 14 nm Node and Key Characteristics
TL;DR: In this paper, the authors provide the design guidelines for 14 nm bulk FinFETs at the 14 nm node, and compare the performance of 14 nm SOI and 14 nm BFTs in terms of scalability, parasitic capacitance, and heat dissipation.
Proceedings ArticleDOI
Self Heating Simulation of Multi-Gate FETs
Wolfgang Molzer,T. Schulz,Weize Xiong,R. Cleavelin,K. Schrufer,Andrew Marshall,Ken Matthews,J. Sedlmeir,Domagoj Siprak,G. Knoblinger,L. Bertolissi,P. Patruno,Jean-Pierre Colinge +12 more
TL;DR: In this article, the authors demonstrate a simplification of the approach to a thermal only problem from which much useful information can be extracted, such as time constants and thermal capacitances for thermal compact models which are usually difficult to extract experimentally may be simulated numerically.
Journal ArticleDOI
Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG
Pragya Kushwaha,K. Bala Krishna,Harshit Agarwal,Sourabh Khandelwal,Juan Pablo Duarte,Chenming Hu,Yogesh Singh Chauhan +6 more
TL;DR: A compact model for the geometry and temperature dependence of Rth in FDSOI transistors is proposed and validated against experimental and Technology Computer Aided Design (TCAD) data.