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Journal ArticleDOI

Modeling of Advanced RF Bulk FinFETs

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TLDR
In this article, the Berkeley short-channel IGFET model-common multi-gate model is improved to account for the impact of substrate coupling on the RF parameters, and the model demonstrates excellent agreement with the measured data over a broad range of frequencies.
Abstract
The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.

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Book ChapterDOI

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Thomas H. Lee
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Journal ArticleDOI

Design Optimization Techniques in Nanosheet Transistor for RF Applications

TL;DR: In this article, the effects of stack spacing and number of stacks on device performance were studied and a substack design for improved RF performance was proposed, which can improve cut-off frequency by approximately 10% and minimum number of substacks and minimum substack spacing should be used.
Journal ArticleDOI

Intermodulation Linearity Characteristics of 14-nm RF FinFETs

TL;DR: In this paper, the authors investigate the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series.
Journal ArticleDOI

Impact of Self-Heating on Negative-Capacitance FinFET: Device-Circuit Interaction

TL;DR: In this paper, the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level is analyzed.
Journal ArticleDOI

Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs

TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
References
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Proceedings ArticleDOI

FinFET technology for analog and RF circuits

TL;DR: How technological options and device design affect the FinFET performance is explained and the challenges and opportunities for both wideband modeling and the design of analog and RF circuits are identified.
Journal ArticleDOI

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

TL;DR: In this paper, an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs is presented.
Journal ArticleDOI

Characterization of RF Noise in UTBB FD-SOI MOSFET

TL;DR: In this paper, the authors report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors.
Proceedings ArticleDOI

BSIM-IMG: Compact model for RF-SOI MOSFETs

TL;DR: In this article, the authors have validated the RF capabilities of BSIM-IMG model which is the latest industry standard compact model for independent double-gate MOSFETs.
Journal ArticleDOI

Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

TL;DR: In this article, the authors analyzed the localized thermal effect caused by self-heating effect (SE) in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors.
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