Modeling of Advanced RF Bulk FinFETs
11 Apr 2018-IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers Inc.)-Vol. 39, Iss: 6, pp 791-794
TL;DR: In this article, the Berkeley short-channel IGFET model-common multi-gate model is improved to account for the impact of substrate coupling on the RF parameters, and the model demonstrates excellent agreement with the measured data over a broad range of frequencies.
Abstract: The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.
Citations
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01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0
207 citations
TL;DR: In this article, the effects of stack spacing and number of stacks on device performance were studied and a substack design for improved RF performance was proposed, which can improve cut-off frequency by approximately 10% and minimum number of substacks and minimum substack spacing should be used.
Abstract: Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency ( ${F}_{{t}}$ ) by ~10% and minimum number of substacks and minimum substack spacing should be used.
24 citations
Cites methods from "Modeling of Advanced RF Bulk FinFET..."
...FinFET has been used successfully from 22- to 7-nm node [2]–[5]....
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TL;DR: In this paper, the authors investigate the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series.
Abstract: This paper investigates the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series. Linearity sweet spots with respect to gate voltage and RF power, as well as its drain voltage dependence, are examined. Key BSIM-CMG model parameters required for simultaneous fitting of dc I–V , S-parameters, and intermodulation distortion are identified and demonstrated. Volterra series analysis shows that distortion resulting from ${V}_{\textsf {DS}}$ derivatives of ${I}_{\textsf {DS}}$ dominates at most biases. A minimum third-order intercept gate voltage ${V}_{\textsf {GS,IP3}}$ of 0.5 V is observed, compared with 0.7 V in a 28-nm high- ${k}$ metal-gate planar device.
11 citations
Cites methods from "Modeling of Advanced RF Bulk FinFET..."
...CMG [14], following the step-by-step extraction strategy of [15] using dc and S-parameter data....
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TL;DR: In this paper, the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level is analyzed.
Abstract: In this work, we analyze the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level. The 3-D thermal TCAD simulations, after careful calibration with measurements, are performed to analyze the impact of SHE in a broad range of frequency. Furthermore, we use the TCAD calibrated BSIM-CMG model to analyze the impact of SHE in NC-FinFET at the circuit level, after including a physics-based model to capture the NC effect. For the first time, we analyze the impact of a nonuniform distribution of temperature dissipated from the channel region to gate-stack in NC-FinFETs. On account of the thermal insulating properties of the gate-stack, the ferroelectric (FE) layer is found to be cooler than the channel region under the impact of SHE. We demonstrate that neglecting that and, hence, using the channel temperature to evaluate the temperature-dependent parameter $\alpha $ (in the Landau–Khalatanikov model of NC effect) of the FE layer result in a significant overestimation of SHE-induced degradations, such as in the NC voltage gain. Based on our TCAD analysis, we propose a relation between gate-stack temperature and the channel temperature and use this to accurately model the $\alpha $ parameter and, hence, SHE in NC-FinFETs. The SHE is found to dominate for both FinFET and NC-FinFET in the gigahertz range, which eventually degrades the performance at the circuit level, which is further confirmed using ring oscillator (RO) simulations.
11 citations
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
Abstract: In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance ( ${g}_{{\text {ds}}}$ ) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ( $\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data.
11 citations
References
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01 Jan 2013
TL;DR: In this article, the authors developed a comprehensive compact SPICE model for a vertical cylindrical gate (CG) MOSFET, which is based on fundamental physics based electrostatics description (Poisson Equation) of the device analytic equations for terminal current and capacitance.
Abstract: The semiconductor industry has relied on accurate device models for analyzing, predicting and innovating integrated circuit design. Multi-gate MOSFET device architectures like FinFETs are beginning to replace their planar MOSFET counterparts at the 22nm technology node to enable continued technology scaling. Vertical cylindrical gate (CG) MOSFET are touted to replace planar MOSFETs as the memory device for DRAM and NAND Flash offering increased area density. New device architectures together with relentless scaling of MOSFETs for performance mean increased complexity and new device physics that need to be comprehended. This new understanding needs to be translated into device models for technology progress. Newer device models also require newer methodologies for model creation process and usage for circuit design. In this thesis we develop a comprehensive compact SPICE model for a CG MOSFET. Relying on fundamental physics based electrostatics description (Poisson Equation) of the device analytic equations for terminal current and capacitance are derived forming the core model. Including all requisite real device effects we validate this model to both numerical simulations (TCAD) and hardware silicon data showing < 1% RMS error when the model is tuned to the data. For channel diameters < 20nm quantum mechanical confinement effects tend to dominate. The complex bias and geometry dependence of the inversion charge centroid is captured through a phenomenological model. This model helps accurate prediction of the reduction in gate capacitance of a CG MOSFET. This model was also extended to carrier confinement in thin channels such as the double gate FET or FinFET. The vertical CG MOSFET exhibits asymmetry w.r.t. source and drain. With the aid of TCAD we propose that non-uniform vertical channel doping and structural differences in the top and bottom (source/drain) junction regions as the major contributors to the asymmetric behavior. We then create a mathematical framework to capture these asymmetries in the compact model developed above. We validate this approach by showing excellent agreement to hardware silicon data from a high voltage vertical CG MOSFET technology. All these models have been incorporated in BSIM-CMG the first industry standard multi-gate MOSFET model. Despite including many complex physical effects the resultant model can be executed in the order of few 10's of secs (per operating point) enabling rapid very large scale integrated circuit design. A compact SPICE model maintains a balance of predictive nature and flexibility with many sub-components describing various physics and tunable parameters in order to capture data from various sources accurately. This could quickly become unmanageable during a model creation process. For this we propose a RF model extraction procedure that does not require any additional sub-circuit elements and takes advantage of advances in parameter optimization tools available today in an efficient manner. We demonstrate this procedure on high frequency data from multiple planar MOSFET technologies discussing various use cases. Using BSIM6, a bulk planar MOSFET compact model the resultant procedure was able to capture silicon data even beyond the cut-off frequency of the MOSFET and predict various RF circuit design figure of merits with great accuracy.
6 citations
"Modeling of Advanced RF Bulk FinFET..." refers background in this paper
...the off-state condition, whereas in the on-state, it is influenced by output conductance of the intrinsic device [18]....
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