Modeling of Subsurface Leakage Current in Low $V_{\mathrm {TH}}$ Short Channel MOSFET at Accumulation Bias
TL;DR: In this article, a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation is presented, which takes drain-to-source voltage, gate-tosource voltage and gate length into account.
Abstract: We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source–drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage ( $V_{\mathrm{ DS}})$ , gate-to-source voltage ( $V_{\mathrm{ GS}})$ , gate length ( $L_{G})$ , substrate doping concentration ( $N_{\mathrm{ sub}})$ , and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.
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TL;DR: In this paper, a surface potential-based compact model for nanowire FETs is presented, which considers 1-D electrostatics along with the effect of multiple energy subbands.
Abstract: We present a surface potential-based compact model for nanowire FETs, which considers 1-D electrostatics along with the effect of multiple energy subbands. The model is valid for any semiconductor material, cross-sectional geometry, and any channel length with transport regimes varying from drift-diffusive to quasi-ballistic. The model captures the phenomenon of quantum capacitance and the effect of temperature. We have validated it with numerical simulations and experimental data for Si, Ge, and InAs nanowires of different geometries. Circuit simulation has also been performed with the model. The physics-based model is accurate and can be used as a tool for analysis and prediction of the effects of geometry scaling, material dependence, and temperature variation on device and circuit characteristics. To the best of our knowledge, this is the first time a compact model for nanowire FETs is being presented, which includes multiple subbands along with geometry scaling while being valid for different degenerate and nondegenerate semiconductor materials.
23 citations
Cites background from "Modeling of Subsurface Leakage Curr..."
...CONTINUED scaling of FETs weakens the gate control and makes devices vulnerable to short-channel effects [1]–[4]....
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TL;DR: In this article, a BSIM-based compact model for a high-voltage MOSFET is presented, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect.
Abstract: A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90-V LDMOS and 40-V VDMOS transistors, and shows excellent agreement.
23 citations
TL;DR: An analytical model, based on the equivalent conductance of the halo device, is developed to understand the anomalous behavior of transconductance in halo implanted MOSFET for linear and saturation regions across both gate and body biases.
Abstract: In this paper, we report anomalous behavior of transconductance ( ${g}_{m}$ ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The ${g}_{m}$ characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the ${g}_{m}$ behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical ${g}_{m}$ behavior. The effect of oxide thickness ( ${T}_{\text {ox}}$ ) variation on ${g}_{m}$ is also studied, which demonstrates a deviation from the conventional $g_{m}$ behavior for halo implanted devices with thicker ${T}_{\text {ox}}$ . A computationally efficient SPICE model is proposed to model ${g}_{m}$ characteristics which shows excellent matching with the measured data.
15 citations
Cites methods from "Modeling of Subsurface Leakage Curr..."
...This model is incorporated in the BSIM6 MOS model [7], which is the latest CMC standard compact model of MOS transistor and employs advanced models for various physical effects [14]–[16]....
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TL;DR: In this article, the authors present a specific compact model for sub-threshold regime leakage current in bulk driven nano-MOSFETs, which is based on PTM.
14 citations
TL;DR: In this paper, the authors present the modeling of zero-threshold voltage (V TH) bulk MOSFET, also called native devices, using enhanced BSIM6 model, which incorporates gate, drain, body biases and channel length as well as channel doping dependency too.
Abstract: In this paper, we present the modeling of zero-threshold voltage (V TH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-V TH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of V DS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (L eff) and channel doping (N SUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.
7 citations
References
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Book•
01 Jan 1987
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION
3,156 citations
"Modeling of Subsurface Leakage Curr..." refers background in this paper
...directly attributed to the barrier lowering induced by VDS, which is similar to drain-induced barrier lowering effect [16]...
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...leakage current in the drain current due to high electric field [10], [16]....
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29 Apr 2003
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
2,281 citations
"Modeling of Subsurface Leakage Curr..." refers background in this paper
...generally independent of the gate length [1]....
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...THERE are various types of leakage currents, such as gate-induced drain leakage (GIDL) current, drain-tobody/source-to-body junction leakage currents [1], and gate leakage current [2], in OFF-state planar MOSFETs....
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IBM1
TL;DR: In this article, an accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitanceversus-voltage curves to quantum-mechanically simulated capacitance-versusvoltage results.
Abstract: Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 /spl Aring/) nMOSFET's is presented, together with experimental verification. An accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitance-versus-voltage curves to quantum-mechanically simulated capacitance-versus-voltage results. The lifetimes of quasibound states and the direct tunneling current are calculated using a transverse-resonant method. These results are used to project an oxide scaling limit of 20 /spl Aring/ before the chip standby power becomes excessive due to tunneling currents,.
784 citations
"Modeling of Subsurface Leakage Curr..." refers background in this paper
...THERE are various types of leakage currents, such as gate-induced drain leakage (GIDL) current, drain-tobody/source-to-body junction leakage currents [1], and gate leakage current [2], in OFF-state planar MOSFETs....
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TL;DR: In this article, a band-to-band tunneling in Si in the drain/gate overlap region was proposed to limit the leakage current to 0.1 pA/µm.
Abstract: Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero V G in thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.
287 citations
"Modeling of Subsurface Leakage Curr..." refers methods in this paper
...GIDL is modeled by using band-to-band tunneling model [3], and it can be reduced by introducing lightly doped drain (LDD) structure to lower the electric field [4]....
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TL;DR: In this paper, the gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described.
Abstract: A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10/sup 14//cm/sup 2/, the LDD and fully overlapped LDD devices exhibit similar GIDL current. >
122 citations
"Modeling of Subsurface Leakage Curr..." refers background or methods in this paper
...GIDL is modeled by using band-to-band tunneling model [3], and it can be reduced by introducing lightly doped drain (LDD) structure to lower the electric field [4]....
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...The GIDL current should increase as the gate bias becomes more negative and it can be effectively suppressed by LDD structure [4]....
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...The peak value of Gaussian doping profile of source (drain) is 1020 cm−3, while that of source (drain) extension is 1019 cm−3 in order to minimize the GIDL effect [4]....
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