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Journal ArticleDOI

Modeling of threshold voltage and subthreshold slope of nanoscale DG MOSFETs

01 Jan 2008-Semiconductor Science and Technology (IOP Publishing)-Vol. 23, Iss: 1, pp 015010
TL;DR: In this article, a 2D analytical model for the threshold voltage and sub-threshold slope of fully depleted symmetric double gate (DG) n-MOSFETs has been presented.
Abstract: Two-dimensional (2D) analytical models for the threshold voltage and subthreshold slope of fully depleted symmetric double gate (DG) n-MOSFETs have been presented in this paper. 2D Poisson's equation has been solved with suitable boundary conditions to obtain the surface potential at the Si/SiO2 interface. The minimum surface potential has been employed to derive analytical expressions for the threshold voltage and subthreshold slope. Also, these expressions have been modified taking into account the effect of bandgap narrowing due to heavy channel doping and quantum-mechanical effects. In addition, the 2D numerical simulation results obtained using the device simulator ATLAS for the surface potential, the threshold voltage and subthreshold slope have been presented. Further our analytical data have been compared with numerical simulation results for various DG MOSFETs, and our analytical simulation results have also been compared with reported experimental data in the literature. A good agreement is observed among the three, ensuring the validity of our present model. The proposed model is simple and makes it easy to understand the influence of physical phenomena such as quantum-mechanical effects on the electrical parameters, such as the threshold voltage, compared to other models published elsewhere.
Citations
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Journal ArticleDOI
TL;DR: In this paper, a two-dimensional model for the threshold voltage of the short-channel double-gate MOSFETs with a vertical Gaussian-like doping profile is proposed.
Abstract: A two-dimensional (2D) model for the threshold voltage of the short-channel double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a vertical Gaussian-like doping profile is proposed in this paper. The evanescent mode analysis has been used to solve the 2D Poisson’s equation to obtain the channel potential function of the device. The minimum surface potential has been used to model the threshold voltage of the DG MOSFETs. Threshold voltage variations against channel length for different device parameters have been demonstrated. The validity of the proposed model is shown by comparing the results with the numerical simulation data obtained by using the commercially available ATLAS™, a 2D device simulator from SILVACO.

57 citations

Journal ArticleDOI
TL;DR: An analytical drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field effect transistors (finFETs) is presented in this article.
Abstract: An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

51 citations


Cites background or methods from "Modeling of threshold voltage and s..."

  • ...The application of the compact model in simulation results of FinFETs demonstrates that the simple Vt shift model due to structural confinement (21), including the second effect of biasindependent quantum degradation gate capacitance [35], [36],...

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  • ...This correction results in an increase in the threshold voltage Vt of DG FinFETs by the following amount [35] [36]:...

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  • ...formed by the physical oxide layer and the capacitance developed within the average distance of Δz inside the silicon from the interface [35], [36]....

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Proceedings ArticleDOI
14 Mar 2009
TL;DR: In this article, a 2D analytical model for the potential function and threshold voltage of symmetric double-gate (DG) MOSFETs with vertical Gaussian doping profile in the channel is presented.
Abstract: The paper presents a 2D analytical model for the potential function and threshold voltage of symmetric Double-Gate (DG) MOSFETs with vertical Gaussian doping profile in the channel.

38 citations


Cites methods from "Modeling of threshold voltage and s..."

  • ...The short channel threshold voltage models of DG MOSFETs presented by Tsormpatzoglou et al [7] and Hamid et al [8] considered the threshold voltage as a gate voltage at which the minimum carrier charge sheet density invQ reaches a value THQ adequate to achieve the device turn on condition....

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Journal ArticleDOI
TL;DR: In this paper, simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the back surface potentials.
Abstract: Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the front and back surface potentials. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Good agreement between the model, simulation, and experimental results were obtained by calibrating the minimum carrier charge density adequate to achieve the turn-on condition.

28 citations


Cites background from "Modeling of threshold voltage and s..."

  • ...of the inversion charge results in an increase of the front gate oxide thickness by [25], [26]...

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  • ...Thus, for complete threshold voltage modeling considering for structural confinement along the silicon thickness direction the lowest-sub-band, the quantum effects are modeled with increasing the threshold voltages Vtf and Vtb by the amount [25], [26]...

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Journal ArticleDOI
TL;DR: An analytical subthreshold swing model is presented for symmetric double-gate (DG) MOSFETs with Gaussian doping profile in vertical direction based on the effective conduction path effect (ECPE) concept, believed to provide a better physical insight and understanding of DG MOSfET devices operating in the subth threshold regime.
Abstract: An analytical subthreshold swing model is presented for symmetric double-gate (DG) MOSFETs with Gaussian doping profile in vertical direction. The model is based on the effective conduction path effect (ECPE) concept of uniformly doped symmetric DG MOSFETs. The effect of channel doping on the subthreshold swing characteristics for non-uniformly doped device has been investigated. The model also includes the effect of various device parameters on the subthreshold swing characteristics of DG MOSFETs. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained by using the commercially available ATLAS™ device simulator. The model is believed to provide a better physical insight and understanding of DG MOSFET devices operating in the subthreshold regime.

22 citations


Cites background from "Modeling of threshold voltage and s..."

  • ...with the following boundary conditions [7]:...

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  • ...[7] presented an analytical model to consider only the effect of channel length on the subthreshold swing parameter of DG-MOSFETs with a doped channel....

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References
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Journal ArticleDOI
Jan W. Slotboom1, H.C. de Graaff1
TL;DR: In this paper, the authors used optical absorption measurements on uniformly doped silicon samples to determine the bandgap in silicon and used the bipolar transistor itself as the vehicle for measuring the band gap in the base.
Abstract: Theory predicts appreciable bandgap narrowing in silicon for impurity concentrations greater than about 1017 cm−3. This effect influences strongly the electrical behaviour of silicon devices, particularly the minority carrier charge storage and the minority carrier current flow in heavily doped regions. The few experimental data known are from optical absorption measurements on uniformly doped silicon samples. New experiments in order to determine the bandgap in silicon are described here. The bipolar transistor itself is used as the vehicle for measuring the bandgap in the base. Results giving the bandgap narrowing (ΔVg0) as a function of the impurity concentration (N) in the base (in the range of 4.1015–2.5 1019 cm−3) are discussed. The experimental values of ΔVg0 as a function of N can be fitted by: δV g0 = V 1 ln N N 0 + ln 2 N N 0 +C where V1, N0 and C are constants. It is also shown how the effective intrinsic carrier concentration (nie) is related with the bandgap narrowing (ΔVg0).

716 citations

Journal ArticleDOI
Kunihiro Suzuki1, Tetsu Tanaka1, Yoshiharu Tosaka1, Hiroshi Horie1, Yoshihiro Arimoto1 
TL;DR: In this paper, a scaling theory for double-gate SOI MOSFETs is presented, which gives guidance for device design that maintains a sub-threshold factor for a given gate length.
Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

550 citations

Journal ArticleDOI
TL;DR: In this paper, a 2D analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the sub-threshold region by solving Poissons equation in a 2-D boundary value problem.
Abstract: A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.

251 citations

Journal ArticleDOI
TL;DR: In this article, a compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs is derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included.
Abstract: A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.

236 citations

Journal ArticleDOI
TL;DR: In this article, the effects of quantum-mechanical (QM) effects on the subthreshold characteristics, including the threshold voltage, of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled.
Abstract: Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/

184 citations