Modeling of threshold voltage for operating point using industry standard BSIM-IMG model
15 Dec 2016-pp 216-219
TL;DR: In this paper, the authors proposed an approach to calculate the threshold voltage for operating point information in the BSIM-IMG model which is the latest industry standard compact model for FDSOI transistors.
Abstract: Threshold voltage is an important device parameter for MOSFET modeling as circuit designer needs to know the threshold voltage to bias the transistor in the required region of operation. In this paper, we have proposed an approach to calculate the threshold voltage for operating point information in the BSIM-IMG model which is the latest industry standard compact model for FDSOI transistors. The BSIM-IMG is the surface potential based model, and therefore threshold voltage is not explicitly available. The proposed model takes care of back-bias and other real device effects (CLM, DIBL etc) accurately. The model is developed to fulfill the demand of semiconductor companies for their commercial SPICE simulators and PDKs. We have shown model comparison with various popular threshold voltage extraction techniques. The model shows very good agreement with the measured data over wide range of device geometries, drain and body biases.
Citations
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TL;DR: Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better results.
Abstract: Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field ( ${E}_{\max}$ ) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness ( ${T}_{\mathrm {fe}}$ ), coercive field ( ${E}_{c}$ ), remnant polarization ( ${P}_{r}$ ), baseline transistor equivalent oxide thickness, supply voltage ( ${V}_{\mathrm {dd}}$ ), threshold voltage ( ${V}_{\mathrm {th}}$ ), and ${E}_{\max}$ . Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio and sub-threshold swing while operating at lower ${V}_{\mathrm {dd}}$ .
27 citations
Cites background from "Modeling of threshold voltage for o..."
...The threshold voltage term Vth in (4) takes care of the flat band voltage [25]....
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TL;DR: In this paper, an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs is presented.
Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.
14 citations
TL;DR: In this article, a hybrid extrapolation threshold voltage extraction method (HEEM) is proposed to extract the real value of threshold voltage from MOSFETs, and the results are verified by extensive 2D TCAD simulation and confirmed analytically at various technology nodes.
Abstract: Threshold voltage (VTH) is the indispensable vital parameter in MOSFET designing, modeling, and operation. Diverse expounds and extraction methods exist to model the on-off transition characteristics of the device. The governing gauge for efficient threshold voltage definition and extraction method can be itemized as clarity, simplicity, precision, and stability throughout the operating conditions and technology node. The outcomes of extraction methods diverge from the exact values due to various short-channel effects (SCEs) and nonidealities present in the device. A new approach to define and extract the real value of VTH of MOSFET is proposed in the manuscript. The subsequent novel enhanced SCE-independent VTH extraction method named “hybrid extrapolation VTH extraction method” (HEEM) is elaborated, modeled, and compared with few prevalent MOSFET threshold voltage extraction methods for validation of the results. All the results are verified by extensive 2D TCAD simulation and confirmed analytically at various technology nodes.
9 citations
Cites background from "Modeling of threshold voltage for o..."
...Hence, we can conclude that the HEEM is equally e ective for both short-channel devices and long-channel devices [26, 27]....
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01 Aug 2017
TL;DR: In this article, the authors proposed a new approach to extract the real value of V TH of MOSFETs, which is the crucial device constraint to model on-off transition characteristics.
Abstract: Threshold voltage (V TH ) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise V TH value of the device is described and evaluated by several estimation techniques. However these assessed values of V TH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. A new approach to extract the real value of V TH of MOSFET is proposed in the manuscript. The subsequent novel enhanced SCE independent V TH extraction method named Hybrid Extrapolation V TH Extraction Method (HEEM) is elaborated, modeled and compared with few prevalent MOSFET threshold voltage extraction methods for validation of the results. All the results are verified by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes.
Cites background from "Modeling of threshold voltage for o..."
...Hence we can conclude that the HEEM is equally effective for both short channel devices and long channel devices [20,21]....
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DOI•
TL;DR: In this article , the performance of a Pentacene organic thin-film transistor (OTFT) for temperature sensing using organic and inorganic dielectrics (low-k dielectric and high-k Dielectrics) such as PVA, SiO, and HfO2 in the saturation region of device operation is analyzed.
Abstract: This study presents a comparative analysis of the performance of a p-type (Pentacene) organic thin-film transistor (OTFT) for temperature sensing using organic and inorganic dielectrics (low-k dielectric and high-k dielectrics) such as PVA, SiO2, and HfO2 in the saturation region of device operation. The device and the channel parameters such as mobility, threshold voltage, etc. are extracted using the conventional extraction approach at a temperature range of 293– 363 K. The simulation findings indicate how these characteristics change as a function of temperature, and hence could be employed in sensing applications. It is realized that the optimum performance is shown by the high-k dielectric (HfO2), where the mobility is $\sim \,\,4.25\times 10^{-3}$ cm2 /Vs, a low subthreshold slope of 59.6 mV/decade, a high ON/OFF ratio close to $9.4\times 10^{16}$ , low contact resistance of 1.1 $\text{G}{\Omega }$ and threshold voltage ( $\text{V}_{{\mathrm {TH}}}$ ) decreases linearly (positive shift) with increasing temperature. The low value of $\text{V}_{{\mathrm {TH}}}$ ensures low operating voltage thus enabling the realization of a low power temperature sensor. It is shown that there is a 104 percentage change in the ON/OFF ratio which leads to the conclusion that the ON/OFF ratio can be a deciding factor in determining the optimum device parameter for sensing applications. Apart from this, the threshold voltage and the subthreshold slope (SS) are also equally important that affect the performance of the sensors. Notably, the temperature coefficient which denotes the change in device parameter per degree change in temperature is calculated for a more comprehensive study. It is observed that the temperature coefficient for drain current is $11.8\times 10^{-3}$ ng a large change in electrical characteristics when the temperature is altered by 1 kelvin.
References
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TL;DR: In this paper, a 3D simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented.
Abstract: A three-dimensional (3-D) "atomistic" simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position.
699 citations
"Modeling of threshold voltage for o..." refers background in this paper
...Due to the presence of ultra-thin BOX, FDSOI transistors has flexibility of tuning threshold voltage without varying channel doping, thus leading to excellent immunity from random dopant fluctuation and threshold voltage variability issues [4]....
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TL;DR: In this article, the authors modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases.
Abstract: In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.
295 citations
"Modeling of threshold voltage for o..." refers methods in this paper
...(v) The Second-derivative (SD) method [20] is proposed to avoid the dependence on the series resistances, it determines threshold voltage as the gate voltage at which the derivative of the trans-conductance is maximum....
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TL;DR: In this article, a detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented, along with the state of the art, requirements, and solutions at the level of materials, transistor, and technology.
Abstract: The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.
205 citations
"Modeling of threshold voltage for o..." refers background in this paper
...However thin BOX allows strong coupling from the drain through the lightly doped substrate and results in poor channel electrostatics [5]....
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TL;DR: In this article, the authors present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control.
Abstract: In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.
90 citations
"Modeling of threshold voltage for o..." refers background in this paper
...current and capacitance) are calculated in terms of surface potential [8]–[10]....
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TL;DR: In this paper, an empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices, which is related to the short-channel threshold voltage rolloff and minimum channel length with and without a substrate bias.
Abstract: This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed.
83 citations
"Modeling of threshold voltage for o..." refers background in this paper
...Presence of thinner gate oxide along with ultra-thin silicon body makes it a scalable structure even beyond 22 nm technology node [2]....
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