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Journal ArticleDOI

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

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TLDR
It is found that Iedge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to Imain, so an accurate, efficient, and scalable model for Iedge is developed.
Abstract
We enhance the capability of industry standard compact model BSIM6 to model the parasitic current $ I_{{\text {edge}}}$ at the shallow trench isolation edge. Accurate, efficient, and scalable model for $ I_{{\text {edge}}}$ is developed by finding the key differences between $ I_{{\text {edge}}}$ and main device drain current ( $ I_{{\text {main}}}$ ). It is found that $ I_{{\text {edge}}}$ has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to $ I_{{\text {main}}}$ . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

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Journal ArticleDOI

BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect

TL;DR: In this article, a BSIM-based compact model for a high-voltage MOSFET is presented, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect.
Journal ArticleDOI

Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs

TL;DR: An improved analytical model for flicker noise in MOSFETs is presented in this paper, which captures the effect of high-trap density in the halo regions of the devices.
Journal ArticleDOI

Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling

TL;DR: An analytical model, based on the equivalent conductance of the halo device, is developed to understand the anomalous behavior of transconductance in halo implanted MOSFET for linear and saturation regions across both gate and body biases.
Journal ArticleDOI

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

TL;DR: In this article, a generalized constant current (GCC) method was proposed to extract threshold voltage and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion.
Journal ArticleDOI

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

TL;DR: In this paper, a generalized constant current (GCC) method was proposed to extract threshold voltage and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion.
References
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Book ChapterDOI

I and J

Book

Fundamentals of Modern VLSI Devices

Yuan Taur, +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI

BSIM6: Analog and RF Compact Model for Bulk MOSFET

TL;DR: The BSIM6 model has been extensively validated with industry data from 40-nm technology node and shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations.
Journal ArticleDOI

Validation of MOSFET model Source–Drain Symmetry

TL;DR: In this paper, the authors present dc and ac tests that verify whether a MOSFET model is symmetric with respect to a source-drain reversal, and also verify the symmetry of gate and bulk currents.
Proceedings ArticleDOI

Shallow trench isolation for advanced ULSI CMOS technologies

TL;DR: In this article, the authors reviewed the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 1/spl mu/m CMOS technologies and described various processing techniques for the steps in the STI flow viz trench definition, corner rounding, gapfill, planarization and well implants.
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