Modeling STI Edge Parasitic Current for Accurate Circuit Simulations
03 Apr 2015-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 34, Iss: 8, pp 1291-1294
TL;DR: It is found that Iedge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to Imain, so an accurate, efficient, and scalable model for Iedge is developed.
Abstract: We enhance the capability of industry standard compact model BSIM6 to model the parasitic current $ I_{{\text {edge}}}$ at the shallow trench isolation edge. Accurate, efficient, and scalable model for $ I_{{\text {edge}}}$ is developed by finding the key differences between $ I_{{\text {edge}}}$ and main device drain current ( $ I_{{\text {main}}}$ ). It is found that $ I_{{\text {edge}}}$ has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to $ I_{{\text {main}}}$ . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.
Citations
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TL;DR: An improved analytical model for flicker noise in MOSFETs is presented in this paper, which captures the effect of high-trap density in the halo regions of the devices.
Abstract: An improved analytical model for flicker noise (1/ $f$ noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.
18 citations
Cites methods from "Modeling STI Edge Parasitic Current..."
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TL;DR: An analytical model, based on the equivalent conductance of the halo device, is developed to understand the anomalous behavior of transconductance in halo implanted MOSFET for linear and saturation regions across both gate and body biases.
Abstract: In this paper, we report anomalous behavior of transconductance ( ${g}_{m}$ ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The ${g}_{m}$ characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the ${g}_{m}$ behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical ${g}_{m}$ behavior. The effect of oxide thickness ( ${T}_{\text {ox}}$ ) variation on ${g}_{m}$ is also studied, which demonstrates a deviation from the conventional $g_{m}$ behavior for halo implanted devices with thicker ${T}_{\text {ox}}$ . A computationally efficient SPICE model is proposed to model ${g}_{m}$ characteristics which shows excellent matching with the measured data.
11 citations
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TL;DR: In this article, a BSIM-based compact model for a high-voltage MOSFET is presented, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect.
Abstract: A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90-V LDMOS and 40-V VDMOS transistors, and shows excellent agreement.
5 citations
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TL;DR: The recent and upcoming enhancements of the industry standard BSIM-BULK model are presented and an analytical model for bulk charge effect, in both current and capacitance, is implemented to improve the model accuracy for transconductance and output conductance.
Abstract: In this work, we present the recent and upcoming enhancements of the industry standard BSIM-BULK (formerly BSIM6) model. BSIM-BULK is the latest body referenced compact model for bulk MOSFETs having a unified core, which is developed by the BSIM group for accurate design of analog and RF circuits. The model satisfies the symmetry test for DC and AC, correctly predicts harmonic slope, and exhibits accurate results for RF and analog simulations. In order to further improve the model accuracy for transconductance $(g_{m})$ and output conductance $(g_{ds})$, an analytical model for bulk charge effect, in both current and capacitance, is implemented. Several other advanced models are added to capture real device physics. These include: parasitic current at the shallow trench isolation edges; leakage current components in zero threshold voltage native devices; new model for NQS to capture the NQS effects up to the millimeter wave regime; self heating effect; and heavily halo implanted MOSFET’s anomalous g m , flicker noise and I DS mismatch. All these enhancements have been implemented to high standards of computational efficiency and robustness.
4 citations
Cites methods from "Modeling STI Edge Parasitic Current..."
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TL;DR: The SPICE model can effectively reflect the variation of current characteristics before and after radiation, and provide a reference to develop a radiation-hardening technology.
Abstract: In order to study the total ionizing dose effects (TID)-induced degradation mechanism of 130 nm partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs , a SPICE model including the TID effects was established with Verilog-A. The total ionizing dose effects will lead to the threshold-voltage shift and the leakage current increase of SOI NMOSFETs . The increase of leakage current in the STI region is the main factor leading to degradation of characteristics of devices, which will form a parasitic transistor. Based on the standard BSIM SOI process model, the SPICE model of leakage current of the STI parasitic transistor is added, and the variation of equivalent gate width and gate oxide thickness caused by radiation-induced trapped charges are considered. The devices with different width-length-ratios and different bias conditions are considered in our experiments, and the model can effectively reflect the variation of current characteristics before and after radiation, and provide a reference to develop a radiation-hardening technology.
3 citations
References
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01 Jan 2012
123,310 citations
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Book•
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IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,655 citations
"Modeling STI Edge Parasitic Current..." refers background in this paper
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IBM1
TL;DR: In this paper, a planarization technique for variable size and pattern factors is presented, which is applied in the shallow trench isolation process which is used in 16-Mb DRAM (dynamic RAM) technology to achieve 05- mu m isolation/device dimensions.
Abstract: A novel planarization technique for variable size and pattern factors is presented It is demonstrated that by the combination of reactive ion etching (RIE) and chemical mechanical polish (CMP), the process window is improved to the extent that the planarization becomes a reality This technique is applied in the shallow trench isolation process which is used in 16-Mb DRAM (dynamic RAM) technology to achieve 05- mu m isolation/device dimensions By a proper combination of RIE and CMP processes, the fundamental problem of tolerance accumulation from deposition and etchback of large film thicknesses is avoided Excellent planarization is achieved in different areas of the DRAM chip with varying isolation sizes and pattern factors, including deep trench integration High gate oxide breakdown yield (comparable to LOCOS isolation), which is indicative of the planarization low defect density, is demonstrated >
89 citations
"Modeling STI Edge Parasitic Current..." refers methods in this paper
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TL;DR: In this paper, the authors present dc and ac tests that verify whether a MOSFET model is symmetric with respect to a source-drain reversal, and also verify the symmetry of gate and bulk currents.
Abstract: This paper presents dc and ac tests that verify whether a MOSFET model is symmetric with respect to a source-drain reversal. The tests are valid in the presence of and also verify the symmetry of gate and bulk currents, and evaluate the symmetry of all components of MOSFET charge models
88 citations
"Modeling STI Edge Parasitic Current..." refers methods in this paper
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TL;DR: In this article, the authors reviewed the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 1/spl mu/m CMOS technologies and described various processing techniques for the steps in the STI flow viz trench definition, corner rounding, gapfill, planarization and well implants.
Abstract: This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 01 /spl mu/m CMOS technologies Various processing techniques are described for the steps in the STI flow viz trench definition, corner rounding, gapfill, planarization and well implants The current capability and scaling requirements for each process step, discussed in the paper, are as follows: (a) Trenches have sidewall angle >/spl sim/80/spl deg/ to maintain trench depth and isolation at narrow space The trench bottom is rounded to minimize stress (b) Pad oxide undercut, prior to liner oxidation in halogen ambient or at high temperature, provides adequate corner rounding to suppress edge leakage, with minimum loss of active area (c) HDP and TEOS-O/sub 3/ CVD oxides can fill 016 /spl mu/m wide trenches free of voids Lower trench aspect ratios (thinner nitride and liner oxide, and shallower trenches), and process improvements allow scaling to smaller dimensions Gapfill process, liner oxide, and thermal cycles are tailored to prevent stress-induced defects, trench sidewall and corner damage (d) CMP step height uniformity is improved by using dummy active areas, nitride overlayer or patterned etchback (e) Optimization of retrograde well and channel stop implants minimizes sensitivity of N/sup +/-P/sup +/ isolation to overlay tolerance and improves latch-up performance
87 citations
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