Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET
14 Oct 2019-pp 9320660
TL;DR: In this article, a unified phenomenological model for insulator capacitance in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET was developed to solve the gate charge density accurately.
Abstract: Lateral nanosheet field-effect-transistor (FET) is now targeting for 3nm CMOS technology node [1], [2]. It is important to see quantization effect at such confined geometry. In this work, we study the geometrical confinement effects in silicon nanosheet. We developed a unified phenomenological model for insulator capacitance (C ins ) in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET to solve the gate charge density accurately. It is observed that multi-subband conduction causes humps in higher order derivatives of charge vs gate voltage characteristics which may affect the performance of analog and RF circuits.
Citations
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DOI•
16 Jul 2022
TL;DR: In this article , the performance of a gate all around field effect transistor (GAA-FET) with varying gate dielectric characteristics with high-k dielectoric oxide materials (Al2O3, HfO2,HfSiO4, SiO2 and Ta2O5, TiO2) across the 3-nm channel length was examined.
Abstract: Semiconductor devices using high k dielectric materials are widely adopted in memory and amplifier applications. Among the semiconductor devices gate all around-FET (GAAFET) is now the latest trend being used instead of other field effect transistors to serve the purpose of reducing the short channel effects (SCE). In this work, we examine the performance of a circular cross-section gate all around-field effect transistor (GAA-FET) with varying gate dielectric characteristics with high-k dielectric oxide materials (Al2O3, HfO2, HfSiO4, SiO2, Ta2O5, TiO2) across the 3-nm channel length. These simulations showed that even though the dielectric constant over the channel increases in value, both ION-IOFF ratio and transconductance upsurge. The obtained results indicated that raising the dielectric constant in a gate oxide reduces subthreshold slope (SS), increases amplification rate, and reduces threshold voltage (VTH) roll-off as well. The Silvaco TCAD ATLAS simulation was calibrated against experimental data from different works of literature. The higher the dielectric constant, the lower the SCEs. It is also found that TiO2 is dominating over the other materials selected for the simulation for a higher value of dielectric constant.
16 Jul 2022
TL;DR: In this paper , the performance of a gate all around field effect transistor (GAA-FET) with varying gate dielectric characteristics with high-k dielectoric oxide materials (Al2O3, HfO2,HfSiO4, SiO2 and Ta2O5, TiO2) across the 3-nm channel length was examined.
Abstract: Semiconductor devices using high k dielectric materials are widely adopted in memory and amplifier applications. Among the semiconductor devices gate all around-FET (GAAFET) is now the latest trend being used instead of other field effect transistors to serve the purpose of reducing the short channel effects (SCE). In this work, we examine the performance of a circular cross-section gate all around-field effect transistor (GAA-FET) with varying gate dielectric characteristics with high-k dielectric oxide materials (Al2O3, HfO2, HfSiO4, SiO2, Ta2O5, TiO2) across the 3-nm channel length. These simulations showed that even though the dielectric constant over the channel increases in value, both ION-IOFF ratio and transconductance upsurge. The obtained results indicated that raising the dielectric constant in a gate oxide reduces subthreshold slope (SS), increases amplification rate, and reduces threshold voltage (VTH) roll-off as well. The Silvaco TCAD ATLAS simulation was calibrated against experimental data from different works of literature. The higher the dielectric constant, the lower the SCEs. It is also found that TiO2 is dominating over the other materials selected for the simulation for a higher value of dielectric constant.
References
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05 Jun 2017
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Abstract: In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.
547 citations
01 Dec 2006
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
160 citations
TL;DR: In this article, a compact physics-based model for the nanoscale gate-all-around MOSFET working in the ballistic limit is presented, where the current through the device is obtained by means of the Landauer approach, being the barrier height the key parameter in the model.
Abstract: We present a compact physics-based model for the nanoscale gate-all-around MOSFET working in the ballistic limit. The current through the device is obtained by means of the Landauer approach, being the barrier height the key parameter in the model. The exact solution of the Poisson's equation is obtained in order to deal with all the operation regions tracing properly the transitions between them.
144 citations
TL;DR: In this article, the effects of source/drain doping density on the ballistic performance of III-V nanowire (NW) n-channel metal-oxide-semiconductor field effect transistors (n-MOSFETs) are explored through atomistic quantum transport simulation.
Abstract: Effects of source/drain (S/D) doping density (N
SD
) on the ballistic performance of III-V nanowire (NW) n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) are explored through atomistic quantum transport simulation. Different III-V materials (InAs, GaAs) and transport directions ( , ) are considered with Si included for benchmarking for a gate length of 13 nm. For III-V's, depending on the operating condition (OFF-current target for a given supply voltage), there exists an optimum N
SD
that maximizes ON-current (I
ON
) by balancing source exhaustion versus tunneling leakage. For InAs, sub-threshold swing degrades significantly with increasing N
SD
due to the light effective mass (m*) and source-drain tunneling, so the optimum N
SD
is low. For GaAs, such dependence is much weaker due to the larger m*, and the optimum N
SD
is higher. With optimized N
SD
's, InAs shows low ballistic I
ON
due to the low density-of-state (DOS) whereas GaAs NW with transport direction shows good ballistic I
ON
due to the improved DOS with still high injection velocity, making it a better candidate for high performance device.
41 citations