# Models and algorithms for bounds on leakage in CMOS circuits

##### Citations

561 citations

### Additional excerpts

...Keywords: leakage power, critical speed, low power scheduling, real-time systems, EDF scheduling, procrastication....

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388 citations

### Cites background from "Models and algorithms for bounds on..."

...stackof four transistors,the reductionin leakagecanbe up to a factorof 20 [14]....

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293 citations

221 citations

### Cites background or methods from "Models and algorithms for bounds on..."

...For gates connected to an NMOS (or PMOS) leakage control transistor, we generate an equivalent circuit to which the transistor stack based leakage model [ 8 ] can be applied....

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...The results were generated using 0.5 m MOS models modified to exaggerate leakage ( m, v) [ 8 ]....

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...... specified in . “All possible leakage states,” is restricted to the set of states permitted by the partially specified input vector and the assignment of value to input . For a network of logic gates, , is defined as a weighted sum of leakage costs for each gate in the fanout cone of input . This avoids the combinatorial explosion that would occur if the gate level definition were applied to the entire network. Details can be found in [ 8 ]....

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...The method used to identify a low-leakage-input vector is documented in detail in [ 8 ]....

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...We propose an approach which does not require multiple threshold voltages or substrate biasing, but takes advantage of leakage behavior in stacks of MOS transistors [ 8 ], [9] to reduce sleep mode leakage while avoiding active mode performance loss....

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187 citations

##### References

21,651 citations

### "Models and algorithms for bounds on..." refers background in this paper

...Identification of a minimum (or maximum) leakage input vector can be shown to be NP-hard by means of a polynomial time transformation from the three-CNF circuit satisfiability problem, which is known to be NP-complete [ 1 ]....

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1,348 citations

560 citations

### "Models and algorithms for bounds on..." refers methods in this paper

...Using the BSIM [ 10 ] transistor model, we have derived a model to predict quiescent voltage levels and leakage current in a stack of transistors....

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298 citations

### "Models and algorithms for bounds on..." refers background in this paper

...The effect of circuit input logic values on leakage was observed by Halter and Najm [ 3 ], but the underlying reasons for this effect were not explained....

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289 citations