Modified surface potential based current modeling of thin silicon channel double gate SOI FinFETs

Computing Surface Potential of Double Gate MOSFET for both Free and Doped Carrier Concentrations

Abstract: Surface potential of symmetric double gate MOSFET is analytically investigated by solving Poisson's equation subject to appropriate boundary conditions considering the presence of both free and doped carriers. Different semiconductors are considered for simulation purpose to find the change in potential w.r.t to the already existing results for Si, and carrier concentrations are modified within feasible limit to observe the variation. Simulations are also carried out at different temperatures in order to account the Joule heat effect at on-chip, and significant variations are observed. Result will play key role in determining drain current through DG MOSFET which satisfies Ortiz-Conde model.

Analytical drain current core model for undoped double gate MOS transistor

Abstract: A new analytical drain current model is proposed for symmetrical undoped double gate MOS transistors. It contains no fitting parameters and is physically-based.

On the Lambert W function

Abstract: The LambertW function is defined to be the multivalued inverse of the functionw →we w . It has many applications in pure and applied mathematics, some of which are briefly described here. We present a new discussion of the complex branches ofW, an asymptotic expansion valid for all branches, an efficient numerical procedure for evaluating the function to arbitrary precision, and a method for the symbolic integration of expressions containingW.

Design of ion-implanted MOSFET's with very small physical dimensions

Abstract: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs

Abstract: A compact physics-based quantum-effects model for symmetrical double-gate (DG) MOSFETs of arbitrary Si-film thickness is developed and demonstrated. The model, based on the quantum-mechanical variational approach, not only accounts for the thin Si-film thickness dependence but also takes into account the gate-gate charge coupling and the electric field dependence; it can be used for FDSOI MOSFETs as well. The analytical solutions, verified via results obtained from self-consistent numerical solutions of the Poisson and Schrodinger equations, provide good physical insight with regard to the quantization and volume inversion due to carrier confinement, which is governed by the Si-film thickness and/or the transverse electric field. A design criterion for achieving beneficial volume-inversion operation in DG devices is quantitatively defined for the first time. Furthermore, the utility of the model for aiding optimal DG device design, including exploitation of the volume-inversion benefit to carrier mobility, is exemplified.

Quantum-mechanical effects in trigate SOI MOSFETs

Abstract: A self-consistent Poisson-Schro/spl uml/dinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm /spl times/ 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections.