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MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs

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TLDR
In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weakinversion region is shown to be the optimum design zone for CMOS 2.4 GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications.
Abstract
In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.

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Journal ArticleDOI

Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 $\upmu \text{W}$ 0.6–4.2 GHz Current-Reuse CMOS LNA

TL;DR: It is shown that FBB boosts the output resistance of a transistor such that the intrinsic gain reduction due to low-supply voltages can be compensated and used to implement a low-noise amplifier (LNA) tailored for ultra-low power (ULP) and ULV applications.
Journal ArticleDOI

Analysis and Demonstration of an IIP3 Improvement Technique for Low-Power RF Low-Noise Amplifiers

TL;DR: This paper describes a linearization method to enhance the third-order distortion performance of a subthreshold common-source cascode low-noise amplifier (LNA) without extra power consumption by using passive components.
Journal ArticleDOI

A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network

TL;DR: A component sharing technique and a component-Q-aware impedance-matching technique are introduced in the proposed LNA circuit that can be configured for multiple narrowband as well as wideband operations while providing simultaneous input matching and output load reconfigurabilty.
Journal ArticleDOI

A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS

TL;DR: A low-imbalance active balun topology is being herein proposed, analyzed in detail, designed, and tested, which achieves a gain tuning range of 45 dB, a noise figure of 3.4 dB, and dissipates 19 mW in the maximum gain condition.
Proceedings ArticleDOI

A tunable Ultra Low Power inductorless Low Noise Amplifier exploiting body biasing of 28 nm FDSOI technology

TL;DR: The potential of the backBiasing to lower the power consumption of more than 30 % compared to a design without back biasing, while keeping similar performance is demonstrated.
References
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Journal ArticleDOI

A 1.5-V, 1.5-GHz CMOS low noise amplifier

TL;DR: In this article, a 1.5 GHz low noise amplifier (LNA) intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6/spl mu/m CMOS process.
Journal ArticleDOI

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

TL;DR: In this paper, a new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used.
Journal ArticleDOI

CMOS low-noise amplifier design optimization techniques

TL;DR: In this article, four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology are reviewed and analyzed: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-consistency with SNIM (PCSNIM) techniques.
Journal ArticleDOI

An MOS transistor model for analog circuit design

TL;DR: A physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits is presented.
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