Multilevel inverters: A literature survey on topologies and control strategies

TL;DR: In this article, the authors present the most important topologies of multilevel inverters, including diode-clamped inverter (neutral-point clamped), capacitor-capped, and cascaded multi-level with separate dc sources.

Abstract: Multilevel inverters have been attracting in favor of academia as well as industry in the recent decade for high-power and medium-voltage energy control. In addition, they can synthesize switched waveforms with lower levels of harmonic distortion than an equivalently rated two-level converter. The multilevel concept is used to decrease the harmonic distortion in the output waveform without decreasing the inverter power output. This paper presents the most important topologies like diode-clamped inverter (neutral- point clamped), capacitor-clamped (flying capacitor), and cascaded multilevel with separate dc sources. This paper also presents the most relevant modulation methods developed for this family of converters: multilevel sinusoidal pulse width modulation, multilevel selective harmonic elimination, and space-vector modulation. Authors strongly believe that this survey article will be very much useful to the researchers for finding out the relevant references in the field of topologies and modulation strategies of multilevel inverter.

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MULTI-LEVEL INVERTER: A LITERATURE SURVEY ON
TOPOLOGIES AND CONTROL STRATEGIES
BINDESHWAR SINGH
1
, NUPUR MITTAL
3
, DR. K.S. VERMA
2
, DR. DEEPENDRA SINGH
2
, S.P. SINGH
1
, , RAHUL
DIXIT
3
, MANVENDRA SINGH
3
, AND AANCHAL BARANWAL
4
1
Asstt Prof., Department of Electrical Engineering, KNIT , Sultanpur
2
Prof., Department of Electrical Engineering, KNIT , Sultanpur
3
M.Tech. scholar ., Department of Electrical Engineering, KNIT, Sultanpur
B.Tech. Scholar, Department of Electrical Engineering, KNIT, Sultanpur
E-mail: bindeshwar.singh2025@gmail.com
ABSTRACT
Multilevel inverters have been attracting in favor of academia as well as industry in the recent decade for
high-power and medium-voltage energy control. In addition, they can synthesize switched waveforms with
lower levels of harmonic distortion than an equivalently rated two-level converter.The multilevel concept is
used to decrease the harmonic distortion in the output waveform without decreasing the inverter power
output. This paper presents the most important topologies like diode-clamped inverter (neutral- point
clamped),capacitor-clamped (flying capacitor), and cascaded multilevel with separate dc sources.This paper
also presents the most relevant modulation methods developed for this family of converters: multilevel
sinusoidal pulsewidth modulation, multilevel selective harmonic elimination, and space-vector
modulation.Authors strongly believe that this survey article will be very much useful to the researchers for
finding out the relevant references in the field of topologies and modulation strategies of multilevel
inverter.
Keywords: Diode Clamped Inverter, Capacitor Clamped Inverter, Cascade H-Bridge Inverter, Modulation
Technique.
1. INTRODUCTION
Numerous industrial applications have begun
to require higher power apparatus in recent years.
Some medium voltage motor drives and utility
applications require medium voltage and megawatt
power level. For a medium voltage grid, it is
troublesome to connect only one power
semiconductor switch directly.As a result, a
multilevel power converter structure has been
introduced as an alternative in high power and
medium voltage situations Subsequently, several
multilevel converter topologies have been
developed. A multilevel converter not only
achieves high power ratings, but also enables the
use of renewable energy sources. The term
multilevel began with the three-level converter. The
advantages of three-level Inverter topology over
conventional two-level topology are:
• The voltage across the switches is only one half of
the DC source voltage;
• The switching frequency can be reduced for the
same switching losses;
• The higher output current harmonics are reduced
by the same switching frequency.
Plentiful multilevel converter topologies have been
proposed during the last two decades.
Moreover, three different major multilevel
converter structures have been reported in the
literature: cascaded H-bridges converter with
separate dc sources, diode clamped (neutral-
clamped), and flying capacitors (capacitor
clamped). Moreover, abundant modulation
techniques have been developed.

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Figure.1: One Phase Leg Of An Inverter With (A)
Two Levels, (B) Three Levels, And (C) N Levels.
Figure.1 shows a schematic diagram of one phase
leg of inverters with different numbers of levels, for
which the action of the power semiconductors is
represented by an ideal switch with several
positions. A two-level inverter generates an output
voltage with two values (levels) with respect to the
negative terminal of the capacitor [see Fig. 1(a)],
while the three-level inverter generates three
voltages, and so on.The most attractive features of
multilevel inverters are as follows.
1. They can generate output voltages with
extremely low distortion and lower
.
2. They draw input current with very low
distortion.
3. They generate smaller common-mode (CM)
voltage, thus reducing the stress in the motor
bearings.In addition, using sophisticated
modulation methods, CM voltages can be
eliminated.
4. They can operate with a lower switching
frequency.
A. DIODE-CLAMPED
INVERTER
The most commonly used multilevel topology is the
diode clamped inverter, in which the diode is used
as the clamping device to clamp the dc bus voltage
so as to achieve steps in the output voltage.Thus,
the main concept of this inverter is to use diodes to
limit the power devices voltage stress. The voltage
over each capacitor and each switch is Vdc. An n
level inverter needs (n-1) voltage sources, 2(n-1)
switching devices and (n-1) (n-2) diodes. By
increasing the number of voltage levels the quality
of the output voltage is improved and the voltage
waveform becomes closer to sinusoidal waveform.
Figure.2a) shows a three-level diode-clamped
converter in which the dc bus consists of two
capacitors, C1, C2. For dc-bus voltage Vdc, the
voltage across each capacitor is Vdc/2 and each
device voltage stress will be limited to one
capacitor voltage level Vdc/2 through clamping
diodes. To explain how the staircase voltage is
synthesized, the neutral point n is considered as the
output phase voltage reference point. There are
three switch combinations to synthesize three-level
voltages across a and n.
1. Voltage level Van= Vdc/2, turn on the
switches S1andS2.
2. Voltage level Van= 0, turn on the switches
S2 and S1′.
3. Voltage level Van= - Vdc/2 turn on the
switches S1′,S2′.
Figure.2(b) shows a five-level diode-clamped
converter in which the dc bus consists of four
capacitors, C1, C2, C3, and C4. For dc-bus voltage
Vdc, the voltage across each capacitor is Vdc/4 and
each device voltage stress will be limited to one
capacitor voltage level Vdc/4 through clamping
diodes.
Figure.2: Diode-Clamped Multilevel Inverter
Circuit Topologies. (A) Three-Level.(B) Five-
Level.
To synthesize 5-level output phase
voltage,switching sequence as given in table 1.
State condition 1 means switch ON and 0 means
switch OFF.
Volt
age
V
ao
Switch State
S
1
S
2
S
3
S
4
S
1’
S
2’
S
3’
S
4’
V
dc
1
1
1
1
0
0
0
0
V
dc
/
2
0
1
1
1
1 0 0 0
0
0
0
1
1
1
1
0
0
-
V
dc
/2
0
0
0
1
1 1 1 0
-V
dc
0
0
0
0
1
1
1
1
Table1: Switching States In One Leg Of The
Five-Level Diode Clamped Inverter -Level
B. CASCADED MULTILEVEL
INVERTER
The concept of this inverter is based on connecting
H-bridge inverters in series to get a sinusoidal
voltage output. The output voltage is the sum of the
voltage that is generated by each cell. The number

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of output voltage levels are 2n+1, where n is the
number of cells. The switching angles can be
chosen in such a way that the total harmonic
distortion is minimized. One of the advantages of
this type of multilevel inverter is that it needs less
number of components comparative to the Diode
clamped or the flying capacitor, so the price and the
weight of the inverter is less than that of the two
types.Figure.3 shows the power circuit for one
phase leg of a three-level and five-level cascaded
inverter.In a 3-level cascaded inverter each single-
phase full-bridge inverter generates three voltages
at the output: +Vdc, 0, -Vdc (zero, positive dc
voltage, and negative dc voltage). This is made
possible by connecting the capacitors.The resulting
output ac voltage swings from -Vdc to +Vdc with
three levels, -2Vdc to +2Vdc.
Figure.3: Single Phase Structures Of Cascaded
Inverter (A) 3-Level, (B)5-Level
C. CAPACITOR CLAMPED INVERTER
The structure of this inverter is similar to that of the
diode-clamped inverter except that instead of using
clamping diodes, the inverter uses capacitors in
their place. The flying capacitor involves series
connection of capacitor clamped switching cells.
This topology has a ladder structure of dc side
capacitors, where the voltage on each capacitor
differs from that of the next capacitor. The voltage
increment between two adjacent capacitor legs
gives the size of the voltage steps in the output
waveform.fig shows single phase n-level
configuration of capacitor clamped inverter. An n-
level inverter will require a total of (n-1)×(n-2)/2
clamping capacitors per phase leg in addition to (n-
1) main dc bus capacitors. The voltage levels and
the arrangements of the flying capacitors in the
FCMLI structure assures that the voltage stress
across each main device is same and is equal to
Vdc/(n-1), for an n-level inverter. The voltage
synthesis in a five-level capacitor-clamped
converter has more flexibility than a diode-clamped
converter. Using Figure.4(b) the voltage of the five-
level phase-leg “a” output with respect to the
neutral point n (i.e.Van), can be synthesized by the
following switch combinations.
1. Voltage level Van= Vdc/2, turn on all upper
switches S1 - S4 .
2. Voltage level Van= Vdc/4, there are three
combinations.
a. Turn on switches S1 , S2 , S3 and
S1′.(Van= Vdc/2 of upper C4‟s - Vdc/4
of C1‟s).
b. Turn on switches S2 , S3 , S4 and
S4′.(Van= 3Vdc/4 of upper C3‟s - Vdc/2
of C4‟s).
c. Turn on switches S1 , S3 , S4 and S3′.
(Van= Vdc/2 of upper C4‟s - 3Vdc/4 or
C3‟s + Vdc/2 of upper C„).
3. Voltage level Van= 0, turn on upper switches
S3 , S4 , and lower switch S1′, S2′.
4. Voltage level Van= -Vdc/4, turn on upper
switch S1 and lower switches S1′, S2′and S3′.
5. Voltage level Van= -Vdc/2, turn on all lower
switches S1′, S2′, S3′ and S4′.
Figure.4: Capacitor-Clamped Multilevel Inverter
Circuit Topologies, (A) 3-Level Inverter (B) 5-
Level Inverter.
2. CLASSIFICATION OF CONTROL
STRATEGIES
The main aim of the modulation strategy of
multilevel inverters is to synthesize the output
voltage as close as possible to the sinusoidal
waveform. Many modulation techniques have been
developed for harmonic reduction and switching
loss minimization. The modulation methods used in
multilevel inverters can be classified according to
switching frequency, as shown in Figure.5.Methods
that work with high switching frequencies have
many commutations for the power semiconductors
in one period of the fundamental output voltage. A
very popular method in industrial applications is the
classic carrier-based sinusoidal PWM (SPWM) that

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uses the phase-shifting technique to reduce the
harmonics in the load voltage. Another interesting
alternative is the SVM strategy, which has been
used in three-level inverters.
Methods that work with low switching
frequencies generally perform one or two
commutations of the power semiconductors during
one cycle of the output voltages, generating a
staircase waveform. Representatives of this family
are the multilevel selective harmonic elimination
and the space-vector control (SVC).
Figure.5:Classification Of Multilevel Modulation
Methods.
MULTILEVEL SINUSOIDAL PWM
The control principle of the SPWM is to use several
triangular carrier signals keeping only one
modulating sinusoidal signal. For a m-level
inverter, (m-1) triangular carriers are needed. The
carriers have the same frequency fc and the same
peak-to-peak amplitude AC. The modulating signal
is a sinusoid of frequency fm and amplitude Am. At
every instant, each carrier is compared with the
modulating signal. Each comparison switches the
switch "on" if the modulating signal is greater than
the triangular carrier assigned to that switch. The
main parameters of the modulation process are:
• The frequency ratio k=fc/fm, where fc is the
frequency of the carriers, and fm is the
frequency of the modulating signal.
• The modulation index M=Am / (m *Ac),
where Am is the amplitude of the modulating
signal, A, is the peak-to-peak amplitude of the
carriers, and m'= (m- 1)/2, where m is the
number of level (which is odd).
Figure.6 shows the typical voltage generated by
one cell for the inverter by comparing a sinusoidal
reference with a triangular carrier signal. A number
of –cascaded cells in one phase with their carriers
shifted by an angle
and using the same
control voltage produce a load voltage with the
smallest distortion.
Figure.6: Inverter Cell Voltages. (A) Output
Voltage And Reference With SPWM.(B) Output
Voltage And Reference With Injection Of
Sinusoidal Third Harmonic.
SPACE VECTOR MODULATION
The basic idea of voltage space vector modulation
is to control the inverter output voltages so that
their Parks representation will be approximately
equals the reference voltage vector. In the case of
two level inverter, the output of each phase will be
either +Vdc/2 or - Vd&2.The SVM technique can
be easily extended to all multilevel inverters.
Figure.7 shows space vectors for the traditional
two-, three-, and five-level inverters. These vector
dia-grams are universal regardless of the type of
multilevel inverter. In other words, Figure.7(c) is
valid for five-level diode-clamped, capacitor-
clamped, or cascaded inverter. The adjacent three
vectors can synthesize a desired voltage vector by
computing the duty cycle( Tj, Tj
+1
and T
j+2
) for
each vector.
V*= ( T
j
V
j
+ T
j+1
V
j+1
+ T
j+2
V
j+2
)/T
Space-vector PWM methods generally have the
following features: good utilization of dc-link
voltage, low current ripple, and relatively easy
hardware implementation by a digital signal
processor (DSP). These features make it suitable
for high-voltage high-power applications. As the
number of levels increases, redundant switching
states and the complexity of selecting switching
states increase dramatically. Some authors have
used decomposition of the five level space-vector
diagram into two three-level space-vector diagrams
with a phase shift to minimize ripples and simplify
control.

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SELECTIVE HARMONIC ELIMINATION-
PWM
Selective Harmonic Elimination (SHE) is an off-
line(precalculated) non carrier based PWM
technique. In this method the basic square-wave
output is "chopped" a number of times, which are
obtained by proper off-line calculations.
Figure.7: Space-Vector Diagram: (A) Two-
Level, (B) Three-Level, And (C) Five-Level
Inverter
Figure.8 shows a generalized quarter-wave
symmetric stepped voltage waveform synthesized
by a (2m+1) -level inverter, where m is the number
of switching angles. By applying Fourier series
analysis, the amplitude of any odd n
th
harmonic of
the stepped waveform can be expressed as (4),
whereas the amplitudes of all even harmonics are
zero
hn =
Where V
k
is the K
th
level of dc voltage, n is an
odd harmonic order, m is the number of switching
angles, and a
k
is the th switching angle. According
to Fig. 16, a
1
to a
m
must satisfy
a
1
< a
2
< a
3
<…….< a
m-1
< a
m
<
To minimize harmonic distortion and to achieve
adjustable amplitude of the fundamental
component, up to m-1 harmonic contents can be
removed from the voltage waveform. In general,
the most significant low-frequency harmonics are
chosen for elimination by properly selecting angles
among different level inverters, and high-frequency
harmonic components can be readily removed by
using additional filter circuits. To keep the number
of eliminated harmonics at a constant level, all
switching angles must be less than
Figure.8: Generalized Stepped - Voltage
Waveform
However, if the switching angles do not satisfy
the condition, this scheme no longer exists. As a
result, this modulation strategy basically provides a
narrow range of modulation index, which is its
main disadvantage.
SPACE VECTOR CONTROL
A conceptually different control method for
multilevel inverters, based on the space-vector
theory, has been introduced. This control strategy,
called SVC, works with low switching frequencies
and does not generate the mean value of the desired
load voltage in every switching interval, as is the
principle of SVM. Figure.9 shows the 311 different
space vectors generated by an 11-level inverter. The
reference load voltage vector V
ref
is also included
in this figure. The main idea in SVC is to deliver to
the load a voltage vector that minimizes the space
error or distance to the reference vector V
ref
. The
high density of vectors produced by the 11-level
inverter (see Fig.9) will generate only small errors
in relation to the reference vector; it is, therefore,