Multiport PDN Optimization With the Newton–Hessian Minimization Method
19 Feb 2021-IEEE Transactions on Microwave Theory and Techniques (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 69, Iss: 4, pp 2098-2109
TL;DR: In this paper, an optimization algorithm using the Hessian minimization method, based on the Newton iteration, is proposed to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair.
Abstract: This article proposes an optimization algorithm using the Hessian minimization method, based on the Newton iteration, to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair. The exact effective decoupling regions are obtained using the Newton iteration method for each decoupling capacitor. The impedance of the IC port is lower than the target impedance no matter where the decoupling capacitor is placed in this region. To optimize specific capacitor placements in this region, the Newton iteration, based on the Hessian matrix, is used to determine the location where the impedance of the IC port is minimized at the antiresonant frequency of the plane pair. This placement optimization algorithm allows for a decoupling design method that can also be applied to a PDN with multiple decoupling capacitors for multiple IC ports. Compared with the method of random selection from within the effective decoupling area, the method proposed here requires fewer decoupling capacitors and less computational time.
Citations
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TL;DR: The proposed transformer network-based reinforcement learning method for power distribution network (PDN) optimization of high bandwidth memory (HBM) can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedance seen at multiple ports.
Abstract: In this article, for the first time, we propose a transformer network-based reinforcement learning (RL) method for power distribution network (PDN) optimization of high bandwidth memory (HBM). The proposed method can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedances seen at multiple ports. An attention-based transformer network is implemented to directly parameterize decap optimization policy. The optimality performance is significantly improved since the attention mechanism has powerful expression to explore massive combinatorial space for decap assignments. Moreover, it can capture sequential relationships between the decap assignments. The computing time for optimization is dramatically reduced due to the reusable network on the positions of probing ports and decap assignment candidates. This is because the transformer network has a context embedding process to capture meta-features including probing ports positions. In addition, the network is trained with randomly generated datasets. The computing time for training and data cost are critically decreased due to the scalability of the network. Due to its shared weight property and the context embedding process, the network can adapt to a larger scale of problems without additional training. For verification, the results are compared with conventional genetic algorithm (GA), random search (RS), and all the previous RL-based methods. As a result, the proposed method outperforms in all the following aspects: optimality performance, computing time, and data efficiency.
5 citations
TL;DR: In this paper , a transformer network-based reinforcement learning (RL) method for power distribution network (PDN) optimization of high bandwidth memory (HBM) is proposed, which can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedances seen at multiple ports.
Abstract: In this article, for the first time, we propose a transformer network-based reinforcement learning (RL) method for power distribution network (PDN) optimization of high bandwidth memory (HBM). The proposed method can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedances seen at multiple ports. An attention-based transformer network is implemented to directly parameterize decap optimization policy. The optimality performance is significantly improved since the attention mechanism has powerful expression to explore massive combinatorial space for decap assignments. Moreover, it can capture sequential relationships between the decap assignments. The computing time for optimization is dramatically reduced due to the reusable network on the positions of probing ports and decap assignment candidates. This is because the transformer network has a context embedding process to capture meta-features including probing ports positions. In addition, the network is trained with randomly generated datasets. The computing time for training and data cost are critically decreased due to the scalability of the network. Due to its shared weight property and the context embedding process, the network can adapt to a larger scale of problems without additional training. For verification, the results are compared with conventional genetic algorithm (GA), random search (RS), and all the previous RL-based methods. As a result, the proposed method outperforms in all the following aspects: optimality performance, computing time, and data efficiency.
3 citations
TL;DR: In this article , a multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs).
Abstract: A multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs). The proposed method is based on barrier methods and can simultaneously handle multiple ball grid array (BGA) devices and capacitor ports on practical power/ground plane pairs of polygonal shapes without restriction in the problem geometry. Semi-analytical expressions are developed for the magnitude of device port impedance that is set as the objective function. The placement optimization problem including constraints of planar boundaries and impedance specifications is cast into a matrix expression that meets Karush–Kuhn Tucker (KKT) conditions and solved through Newton–Raphson (N–R) iterations. The convergence of iterations is ensured by guaranteeing the positive definiteness of the system matrix through the Levenberg–Marquardt algorithm. Mutual coupling among multiple ports and discrete components of the problem domain is accounted for via matrix calculus techniques applied to the partial derivatives of optimization variables. The derivatives are evaluated accurately exploiting the semi-analytical relations developed for the distributed planar impedance. The proposed method is tested with several examples, and the results are observed to be in good agreement with those obtained from a numerical electromagnetic (EM) simulator while yielding significant speed-up.
2 citations
TL;DR: In this article , a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5D integrated circuit (IC) designs.
Abstract: Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.
1 citations
01 Dec 2022
TL;DR: In this paper , a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5D integrated circuit (IC) designs.
Abstract: Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.
1 citations
References
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TL;DR: A design methodology for placing on-chip decoupling capacitors is presented and a maximum effective radius is shown to exist for each on- chip decoupled capacitor.
Abstract: Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.
98 citations
IBM1
TL;DR: Capacitor values and quantities are calculated using time and frequency domain techniques in this article, where the authors propose a method for decoupling capacitors to reduce EMC/EMI radiated noise.
Abstract: CMOS circuits on printed circuit boards with continuous power planes require decoupling capacitors to keep power supply within specification, provide signal integrity and reduce EMC/EMI radiated noise. Capacitor values and quantities are calculated using time and frequency domain techniques.
92 citations
TL;DR: In this article, a closed-form expression for the impedance Z matrix of a rectangular power bus structure was obtained by reducing the original double infinite series into a single infinite series under an approximation.
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87 citations
TL;DR: The proposed method is a primary attempt to introduce image feature and background regions decomposition strategies in the field of multi-focus image fusion and outperforms the existing image fusion methods in both visual perception and objective evaluations.
Abstract: In this paper, a Hessian matrix based multi-focus image fusion method is proposed. First, the integral map is introduced for fast compute the Hessian matrix of source images at different scales, and the multi-scale Hessian matrix of source image is obtained. Second, the multi-scale Hessian matrix is used to decompose each source image into two kinds of regions: the feature and background regions. In order to improve the fusion performance, two new focus measures based on the multi-scale Hessian matrix and two different fusion strategies for both feature and background regions are utilized to obtain the initial decision maps, respectively. Finally, the final decision map for image fusion is achieved by post-processing on the results of the previous step. The proposed method is a primary attempt to introduce image feature and background regions decomposition strategies in the field of multi-focus image fusion. The experimental results also show that our method outperforms the existing image fusion methods in both visual perception and objective evaluations.
47 citations
10 Dec 2002
TL;DR: In this paper, the concept of bypass quality factor (BQF) and bypass resistor (BR) is introduced, and different options are shown to set (increase) the ESR of bypass capacitors.
Abstract: Power-distribution networks need to provide impedance response with specified shape/value over a wide frequency band. Bypass capacitors with different values, and capacitors and planes may create resonance peaks, unless the capacitor parameters are selected properly. Distributed matched bypassing (DMB) is suggested to create a smooth impedance profile. DMB requires components with Q/spl Lt/1, which in turn requires user-defined ESR. Different options are shown to set (increase) the ESR of bypass capacitors. The concepts of bypass quality factor (BQF) and bypass resistor (BR) are introduced.
45 citations