Multiport PDN Optimization With the Newton–Hessian Minimization Method
19 Feb 2021-IEEE Transactions on Microwave Theory and Techniques (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 69, Iss: 4, pp 2098-2109
TL;DR: In this paper, an optimization algorithm using the Hessian minimization method, based on the Newton iteration, is proposed to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair.
Abstract: This article proposes an optimization algorithm using the Hessian minimization method, based on the Newton iteration, to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair. The exact effective decoupling regions are obtained using the Newton iteration method for each decoupling capacitor. The impedance of the IC port is lower than the target impedance no matter where the decoupling capacitor is placed in this region. To optimize specific capacitor placements in this region, the Newton iteration, based on the Hessian matrix, is used to determine the location where the impedance of the IC port is minimized at the antiresonant frequency of the plane pair. This placement optimization algorithm allows for a decoupling design method that can also be applied to a PDN with multiple decoupling capacitors for multiple IC ports. Compared with the method of random selection from within the effective decoupling area, the method proposed here requires fewer decoupling capacitors and less computational time.
Citations
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TL;DR: The proposed transformer network-based reinforcement learning method for power distribution network (PDN) optimization of high bandwidth memory (HBM) can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedance seen at multiple ports.
Abstract: In this article, for the first time, we propose a transformer network-based reinforcement learning (RL) method for power distribution network (PDN) optimization of high bandwidth memory (HBM). The proposed method can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedances seen at multiple ports. An attention-based transformer network is implemented to directly parameterize decap optimization policy. The optimality performance is significantly improved since the attention mechanism has powerful expression to explore massive combinatorial space for decap assignments. Moreover, it can capture sequential relationships between the decap assignments. The computing time for optimization is dramatically reduced due to the reusable network on the positions of probing ports and decap assignment candidates. This is because the transformer network has a context embedding process to capture meta-features including probing ports positions. In addition, the network is trained with randomly generated datasets. The computing time for training and data cost are critically decreased due to the scalability of the network. Due to its shared weight property and the context embedding process, the network can adapt to a larger scale of problems without additional training. For verification, the results are compared with conventional genetic algorithm (GA), random search (RS), and all the previous RL-based methods. As a result, the proposed method outperforms in all the following aspects: optimality performance, computing time, and data efficiency.
5 citations
TL;DR: In this paper , a transformer network-based reinforcement learning (RL) method for power distribution network (PDN) optimization of high bandwidth memory (HBM) is proposed, which can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedances seen at multiple ports.
Abstract: In this article, for the first time, we propose a transformer network-based reinforcement learning (RL) method for power distribution network (PDN) optimization of high bandwidth memory (HBM). The proposed method can provide an optimal decoupling capacitor (decap) design to maximize the reduction of PDN self- and transfer impedances seen at multiple ports. An attention-based transformer network is implemented to directly parameterize decap optimization policy. The optimality performance is significantly improved since the attention mechanism has powerful expression to explore massive combinatorial space for decap assignments. Moreover, it can capture sequential relationships between the decap assignments. The computing time for optimization is dramatically reduced due to the reusable network on the positions of probing ports and decap assignment candidates. This is because the transformer network has a context embedding process to capture meta-features including probing ports positions. In addition, the network is trained with randomly generated datasets. The computing time for training and data cost are critically decreased due to the scalability of the network. Due to its shared weight property and the context embedding process, the network can adapt to a larger scale of problems without additional training. For verification, the results are compared with conventional genetic algorithm (GA), random search (RS), and all the previous RL-based methods. As a result, the proposed method outperforms in all the following aspects: optimality performance, computing time, and data efficiency.
3 citations
TL;DR: In this article , a multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs).
Abstract: A multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs). The proposed method is based on barrier methods and can simultaneously handle multiple ball grid array (BGA) devices and capacitor ports on practical power/ground plane pairs of polygonal shapes without restriction in the problem geometry. Semi-analytical expressions are developed for the magnitude of device port impedance that is set as the objective function. The placement optimization problem including constraints of planar boundaries and impedance specifications is cast into a matrix expression that meets Karush–Kuhn Tucker (KKT) conditions and solved through Newton–Raphson (N–R) iterations. The convergence of iterations is ensured by guaranteeing the positive definiteness of the system matrix through the Levenberg–Marquardt algorithm. Mutual coupling among multiple ports and discrete components of the problem domain is accounted for via matrix calculus techniques applied to the partial derivatives of optimization variables. The derivatives are evaluated accurately exploiting the semi-analytical relations developed for the distributed planar impedance. The proposed method is tested with several examples, and the results are observed to be in good agreement with those obtained from a numerical electromagnetic (EM) simulator while yielding significant speed-up.
2 citations
TL;DR: In this article , a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5D integrated circuit (IC) designs.
Abstract: Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.
1 citations
01 Dec 2022
TL;DR: In this paper , a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5D integrated circuit (IC) designs.
Abstract: Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.
1 citations
References
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03 Jan 2006
TL;DR: This work proposes several closed-form solutions for power distribution network optimization and analysis which explicitly take into consideration the mesh topology of modern power-ground networks, and has essentially zero runtime for global power grids, and is therefore usable for layout optimization.
Abstract: With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power/ground distribution networks poses a difficult problem in modern IC design. We propose several closed-form solutions for power distribution network optimization and analysis which explicitly take into consideration the mesh topology of modern power-ground networks. Our analysis and optimization methods have essentially zero runtime for global power grids, and are therefore usable for layout optimization. Experimental validation shows that our IR drop estimation method has almost perfect correlation with true IR drop. Our closed-form sizing solutions save up to 32% area while preserving the peak IR drop; alternatively, we can reduce peak IR drop by up to 33% while preserving the total area of the power distribution network. Our iterated incremental power distribution network improvement technique achieves up to 33% reduction (in one iteration) in peak IR drop over uniformly sized meshes. We also introduce a measure for robustness of power distribution networks to current and process variations.
20 citations
29 Oct 2001
TL;DR: In this paper, a measure for the evaluation of effectiveness of decoupling capacitors placed on package or board structures is presented, where the decoupled capacitors are placed to reduce voltage fluctuations and maintain power and signal integrity.
Abstract: Decoupling capacitors on packages and printed circuit boards are often essential to reduce voltage fluctuations and maintain power and signal integrity. This paper presents a measure for the evaluation of effectiveness of decoupling capacitors placed on package or board structures.
20 citations
TL;DR: In this article, the authors presented a modeling approach for power/ground planes with decoupling capacitors based on the resonant cavity model, where decoupled capacitors are divided into segments according to port coefficients, capacitance, number of decouplings, and the frequency response of each mode of the model.
Abstract: Based on the resonant cavity model, this paper presents a modeling approach for power/ground planes with decoupling capacitors. A bare plane pair is first modeled by the resonant cavity model. Then, decoupling capacitors are divided into segments according to port coefficients, capacitance, the number of decoupling capacitors, and the frequency response of each mode of the resonant cavity model. To get the model of the plane pair with decoupling capacitors, divided segments are incorporated into the resonant cavity model. By this way, not only the influence of decoupling capacitors on each single mode, but also the frequency responses of capacitors in each mode can be reflected. By being incorporated with the segmentation method and the physics-based modeling method, this modeling method can be extended to handle the irregular-shaped and multilayered power/ground plane with capacitors, respectively. Based on the impedance distribution throughout the whole power/ground plane pair, the effective decoupling radius of a capacitor and its variation trends with frequency, capacitance, and parasitic parameters are extracted and analyzed.
17 citations
01 Sep 2010
TL;DR: In this paper, the effect of physical distance on the power supply noise is investigated and a design methodology for simultaneous placement of the on-chip voltage regulators and decoupling capacitors is also described.
Abstract: The effective design of power distribution networks has become highly challenging with each technology generation. The power delivery network is becoming large, making the system analysis process computationally complex. The large number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. To fully exploit the on-chip power supplies and decoupling capacitors, a new design methodology is required to simultaneously design the power distribution network that considers all of the power supplies and decoupling capacitors. Interactions among the power supplies, decoupling capacitors, and active circuitry are investigated in this paper utilizing a computationally efficient methodology. The effect of physical distance on the power supply noise is investigated. A design methodology for simultaneous placement of the on-chip voltage regulators and decoupling capacitors is also described in this paper. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.
13 citations
TL;DR: Using the driving-point impedance (viewed from the device pin) as a metric, a new method is presented for the placement of decoupling capacitors in parallel-plate power ground pairs of high-speed circuits by formulated in the form of a transcendental function.
Abstract: With rapidly increasing switching speeds and surge current requirements, placement of local decoupling capacitors is becoming critically important in high-speed low-power designs. In this paper, utilizing the driving-point impedance (viewed from the device pin) as a metric, a new method is presented for the placement of decoupling capacitors in parallel-plate power ground pairs of high-speed circuits. In the proposed approach, instead of using the traditional trial-and-error method to identify an appropriate placement distance, the process is formulated in the form of a transcendental function. The resulting function is solved using Newton–Raphson (N-R) iterations to give a direct solution for the distance. Also, an analytical representation based on Hankel functions for the driving point impedance and its derivatives is developed to speed up the N-R iterations. The proposed method is validated by comparing the results with the full-wave electromagnetic simulations.
13 citations