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Journal ArticleDOI

Myrinet: a gigabit-per-second local area network

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TLDR
The Myrinet local area network employs the same technology used for packet communication and switching within massively parallel processors, but with the highest performance per unit cost of any current LAN.
Abstract
The Myrinet local area network employs the same technology used for packet communication and switching within massively parallel processors. In realizing this distributed MPP network, we developed specialized communication channels, cut-through switches, host interfaces, and software. To our knowledge, Myrinet demonstrates the highest performance per unit cost of any current LAN. >

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Citations
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Journal ArticleDOI

The CMS experiment at the CERN LHC

S. Chatrchyan, +3175 more
TL;DR: The Compact Muon Solenoid (CMS) detector at the Large Hadron Collider (LHC) at CERN as mentioned in this paper was designed to study proton-proton (and lead-lead) collisions at a centre-of-mass energy of 14 TeV (5.5 TeV nucleon-nucleon) and at luminosities up to 10(34)cm(-2)s(-1)
Journal ArticleDOI

A scalable, commodity data center network architecture

TL;DR: This paper shows how to leverage largely commodity Ethernet switches to support the full aggregate bandwidth of clusters consisting of tens of thousands of elements and argues that appropriately architected and interconnected commodity switches may deliver more performance at less cost than available from today's higher-end solutions.
Book

Principles and Practices of Interconnection Networks

TL;DR: This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies, allowing a designer to see all the steps of the process from abstract design to concrete implementation.
Journal ArticleDOI

A high-performance, portable implementation of the MPI message passing interface standard

TL;DR: The MPI Message Passing Interface (MPI) as mentioned in this paper is a standard library for message passing that was defined by the MPI Forum, a broadly based group of parallel computer vendors, library writers, and applications specialists.

Portable implementation of the mpi message passing interface standard

TL;DR: The MPI Message Passing Interface (MPI) as discussed by the authors is a standard library for message passing that was defined by the MPI Forum, a broadly based group of parallel computer vendors, library writers, and applications specialists.
References
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Journal ArticleDOI

Multicomputers: message-passing concurrent computers

TL;DR: A status report on the architecture and programming of a family of concurrent computers that are organized as ensembles of small programmable computers called nodes, connected by a message-passing network, each with its own private memory is provided in this article.

Pipeline synchronization

J.N. Seizovic
TL;DR: The technique can sustain maximum communication bandwidth while achieving an arbitrarily low, non-zero probability of synchronization failure, P/ sub f, with the price in both latency and chip area being /spl Oscr/(log 1/P/sub f/).
Journal ArticleDOI

Atomic: A High-Speed Local Communication Architecture

TL;DR: The architecture and performance of ATOMIC is described, which adds a general routing capability to the native Mosaic wormhole routing through store-and-forward and path concatenation and is flexible both in topology and functionality.
Journal ArticleDOI

An integration of network communication with workstation architecture

TL;DR: A workstation may be thought of as a group of cooperatively connected subsystems that are used to create a small--scale Gigabit LAN to which these subsystems are attached as nodes, and the architectural focus of such a workstation shifts towards its internal LAN.

A family of routing and communication chips based on the Mosaic

TL;DR: The speciications, internal design, and performance characteristics of the latest series of Caltech Mesh-Routing Chips (MRCs), slack-protocol-conversion chips, and router-interface chips are described.
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