Nanowire-based programmable architectures
01 Jul 2005-ACM Journal on Emerging Technologies in Computing Systems (ACM)-Vol. 1, Iss: 2, pp 109-162
TL;DR: This work develops nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices.
Abstract: Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.
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Book•
02 Nov 2007
TL;DR: This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology.
Abstract: The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.
· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways
531 citations
Book•
18 Apr 2008TL;DR: This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures.
Abstract: Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.
491 citations
TL;DR: This novel nanotransistor technology makes way for a simple and compact hardware platform that can be flexibly reconfigured during operation to perform different logic computations yielding unprecedented circuit design flexibility.
Abstract: Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce s...
349 citations
TL;DR: It is demonstrated here that 14 of 16 Boolean functions can be realized with a single BRS or CRS cell in at most three sequential cycles, making logic-in-memory applications feasible.
Abstract: The realization of logic operations within passive crossbar memory arrays is a promising approach to expand the fields of application of such architectures. Material implication was recently suggested as the basic function of memristive crossbar junctions, and single bipolar resistive switches (BRS) as well as complementary resistive switches (CRS) were shown to be capable of realizing this logical functionality. Based on a systematic analysis of the Boolean functions, we demonstrate here that 14 of 16 Boolean functions can be realized with a single BRS or CRS cell in at most three sequential cycles. Since the read-out step is independent of the logic operation steps, the result of the logic operation is directly stored to memory, making logic-in-memory applications feasible.
329 citations
TL;DR: This work proposes to mitigate device shortcomings and exploit their dynamical character by building self-organizing, self-healing networks that implement massively parallel computations, useful for complex pattern recognition problems.
Abstract: Nanodevices have terrible properties for building Boolean logic systems: high defect rates, high variability, high death rates, drift, and (for the most part) only two terminals. Economical assembly requires that they be dynamical. We argue that strategies aimed at mitigating these limitations, such as defect avoidance/reconfiguration, or applying coding theory to circuit design, present severe scalability and reliability challenges. We instead propose to mitigate device shortcomings and exploit their dynamical character by building self-organizing, self-healing networks that implement massively parallel computations. The key idea is to exploit memristive nanodevice behavior to cheaply implement adaptive, recurrent networks, useful for complex pattern recognition problems. Pulse-based communication allows the designer to make trade-offs between power consumption and processing speed. Self-organization sidesteps the scalability issues of characterization, compilation and configuration. Network dynamics supplies a graceful response to device death. We present simulation results of such a network—a self-organized spatial filter array—that demonstrate its performance as a function of defects and device variation.
276 citations
Cites background from "Nanowire-based programmable archite..."
...…that must be configured to implement the desired functionality (Heath et al 1998, Williams and Kuekes 2000, Kuekes and Williams 2002, DeHon 2003, Stan et al 2003, Ziegler and Stan 2003, Snider et al 2004, DeHon 2005, Ma et al 2005, Snider 2005, Snider et al 2005, Strukov and Likharev 2005)....
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References
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TL;DR: Studies carried out with different conditions and catalyst materials confirmed the central details of the growth mechanism and suggest that well-established phase diagrams can be used to predict rationally catalyst materials and growth conditions for the preparation of nanowires.
Abstract: A method combining laser ablation cluster formation and vapor-liquid-solid (VLS) growth was developed for the synthesis of semiconductor nanowires. In this process, laser ablation was used to prepare nanometer-diameter catalyst clusters that define the size of wires produced by VLS growth. This approach was used to prepare bulk quantities of uniform single-crystal silicon and germanium nanowires with diameters of 6 to 20 and 3 to 9 nanometers, respectively, and lengths ranging from 1 to 30 micrometers. Studies carried out with different conditions and catalyst materials confirmed the central details of the growth mechanism and suggest that well-established phase diagrams can be used to predict rationally catalyst materials and growth conditions for the preparation of nanowires.
4,405 citations
TL;DR: Single-nanowire photoluminescent, electrical transport and electroluminescence measurements show the unique photonic and electronic properties of these nanowire superlattices, and suggest potential applications ranging from nano-barcodes to polarized nanoscale LEDs.
Abstract: The assembly of semiconductor nanowires and carbon nanotubes into nanoscale devices and circuits could enable diverse applications in nanoelectronics and photonics1. Individual semiconducting nanowires have already been configured as field-effect transistors2, photodetectors3 and bio/chemical sensors4. More sophisticated light-emitting diodes5 (LEDs) and complementary and diode logic6,7,8 devices have been realized using both n- and p-type semiconducting nanowires or nanotubes. The n- and p-type materials have been incorporated in these latter devices either by crossing p- and n-type nanowires2,5,6,9 or by lithographically defining distinct p- and n-type regions in nanotubes8,10, although both strategies limit device complexity. In the planar semiconductor industry, intricate n- and p-type and more generally compositionally modulated (that is, superlattice) structures are used to enable versatile electronic and photonic functions. Here we demonstrate the synthesis of semiconductor nanowire superlattices from group III–V and group IV materials. (The superlattices are created within the nanowires by repeated modulation of the vapour-phase semiconductor reactants during growth of the wires.) Compositionally modulated superlattices consisting of 2 to 21 layers of GaAs and GaP have been prepared. Furthermore, n-Si/p-Si and n-InP/p-InP modulation doped nanowires have been synthesized. Single-nanowire photoluminescence, electrical transport and electroluminescence measurements show the unique photonic and electronic properties of these nanowire superlattices, and suggest potential applications ranging from nano-barcodes to polarized nanoscale LEDs.
2,709 citations
Book•
21 May 2004
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Abstract: For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.
2,355 citations
TL;DR: It is shown that nanowires can be assembled into parallel arrays with control of the average separation and, by combining fluidic alignment with surface-patterning techniques, that it is also possible to control periodicity.
Abstract: One-dimensional nanostructures, such as nanowires and nanotubes, represent the smallest dimension for efficient transport of electrons and excitons and thus are ideal building blocks for hierarchical assembly of functional nanoscale electronic and photonic structures. We report an approach for the hierarchical assembly of one-dimensional nanostructures into well-defined functional networks. We show that nanowires can be assembled into parallel arrays with control of the average separation and, by combining fluidic alignment with surface-patterning techniques, that it is also possible to control periodicity. In addition, complex crossed nanowire arrays can be prepared with layer-by-layer assembly with different flow directions for sequential steps. Transport studies show that the crossed nanowire arrays form electrically conducting networks, with individually addressable device function at each cross point.
2,288 citations
"Nanowire-based programmable archite..." refers background or methods in this paper
...Conduction through lightly doped NWs can be controlled via an electrical .eld like Field-Effect Transistors (FETs) [Huang et al. 2001]....
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...2.2 Assembly Langmuir-Blodgett (LB) .ow techniques can be used to align a set of NWs into a single orientation, close pack them, and transfer them onto a surface [Huang et al. 2001; Whang et al. 2003a] (see Figure 4)....
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...The LB step can be rotated and repeated so that we get multiple layers of NWs [Huang et al. 2001; Whang et al. 2003a] such as crossed NWs for building a crossbar array or memory core (Section 4.1)....
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