Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
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TLDR
A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.Abstract:
All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.read more
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Journal ArticleDOI
MoS2 transistors with 1-nanometer gate lengths
Sujay B. Desai,Sujay B. Desai,Surabhi R. Madhvapathy,Surabhi R. Madhvapathy,Angada B. Sachid,Angada B. Sachid,Juan Pablo Llinas,Juan Pablo Llinas,Qingxiao Wang,Geun Ho Ahn,Geun Ho Ahn,Gregory Pitner,Moon J. Kim,Jeffrey Bokor,Jeffrey Bokor,Chenming Hu,H.-S. Philip Wong,Ali Javey,Ali Javey +18 more
TL;DR: Molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode are demonstrated, which exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106.
Journal ArticleDOI
Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors
TL;DR: In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue.
Journal ArticleDOI
Rise of silicene: A competitive 2D material
Jijun Zhao,Hongsheng Liu,Zhi-Ming Yu,Ruge Quhe,Ruge Quhe,Si Zhou,Yangyang Wang,Cheng-Cheng Liu,Hongxia Zhong,Nannan Han,Jing Lu,Yugui Yao,Kehui Wu +12 more
TL;DR: In this paper, a comprehensive review of all the important theoretical and experimental advances on silicene to date, from the basic theory of intrinsic properties, experimental synthesis and characterization, modulation of physical properties by modifications, and finally to device explorations is presented.
Journal ArticleDOI
Two-dimensional materials and their prospects in transistor electronics
TL;DR: A wish list of properties for a good transistor channel material is composed and to what extent the two-dimensional materials fulfill the criteria of the list is examined and a balanced view of both the pros and cons of these devices is provided.
Journal ArticleDOI
Junctionless nanowire transistor (JNT): Properties and design guidelines
Abhinav Kranti,Ran Yan,Chi-Woo Lee,Isabelle Ferain,Ran Yu,N. Dehdashti Akhavan,Pedram Razavi,Jean-Pierre Colinge +7 more
TL;DR: In this article, a junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices using bulk conduction instead of surface channel.
References
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Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
Ge/Si nanowire heterostructures as high-performance field-effect transistors
TL;DR: Comparison of the intrinsic switching delay, τ = CV/I, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFets.
Journal ArticleDOI
A review of some charge transport properties of silicon
TL;DR: In this article, the present knowledge of charge transport properties in silicon, with special emphasis on their application in the design of solid-state devices, is reviewed, and most attention is devoted to experimental findings in the temperature range around 300 K and to high-field properties.
Journal ArticleDOI
Junctionless multigate field-effect transistor
Chi-Woo Lee,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Jean-Pierre Colinge +5 more
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Book
FinFETs and Other Multi-Gate Transistors
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.