NCFET Design Considering Maximum Interface Electric Field
01 Aug 2018-IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers Inc.)-Vol. 39, Iss: 8, pp 1254-1257
TL;DR: Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better results.
Abstract: Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field ( ${E}_{\max}$ ) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness ( ${T}_{\mathrm {fe}}$ ), coercive field ( ${E}_{c}$ ), remnant polarization ( ${P}_{r}$ ), baseline transistor equivalent oxide thickness, supply voltage ( ${V}_{\mathrm {dd}}$ ), threshold voltage ( ${V}_{\mathrm {th}}$ ), and ${E}_{\max}$ . Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio and sub-threshold swing while operating at lower ${V}_{\mathrm {dd}}$ .
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TL;DR: In this paper, the authors present a unique view of the field of negative capacitance electronics from the ferroelectric materials perspective, concluding that HfO2-based ferroelectrics are currently most promising for applications in electronics.
Abstract: Negative capacitance in ferroelectric materials has been suggested as a solution to reduce the power dissipation of electronics beyond fundamental limits. The discovery of ferroelectricity and negative capacitance in the widely used class of HfO2-based materials has since sparked large research efforts to utilize these effects in ultra-low power transistors. While significant progress has been made in the basic understanding of ferroelectric negative capacitance in recent years, the development of practical devices has seen limited success so far. Here, we present a unique view of the field of negative capacitance electronics from the ferroelectric materials perspective. Starting from the basic principles of ferroelectric negative capacitance, we discuss the desirable characteristics of a negative capacitance material, concluding that HfO2-based ferroelectrics are currently most promising for applications in electronics. However, we emphasize that material non-idealities can complicate and in some cases even inhibit the design and fabrication of practical negative capacitance devices using HfO2-based ferroelectrics. Finally, we review the recent progress on experimental devices and give an outlook on the future direction of the field. In particular, further investigations of the microscopic structure of HfO2-based ferroelectrics are needed to provide an insight into the origin of negative capacitance in this material system and to enable predictive device design.
75 citations
TL;DR: A new approach using multi-layer FE to engineer the shape of negative-capacitance field-effect transistor is discussed, and the results show that it leads to better sub-threshold swing as well as lower power supply.
Abstract: Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance ( ${C}_{\textsf {fe}}$ ) and the underlying MOS transistor ( ${C}_{\textsf {MOS}}$ ). Since both ${C}_{\textsf {MOS}}$ and ${C}_{\textsf {fe}}$ have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of ${C}_{\textsf {fe}}$ . The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply ${V}_{\textsf {dd}}$ compared with a prototype single-layer negative-capacitance field-effect transistor.
65 citations
Cites background from "NCFET Design Considering Maximum In..."
...Recognizing that C f e is a non-linear bias dependent capacitor which is negative at P f e = 0 and becomes positive when s-curve turns around the critical polarization, Pc ≈ Pr / √ 3 [9], Fig....
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TL;DR: In this paper, the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node was investigated.
Abstract: We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations.
32 citations
Cites background from "NCFET Design Considering Maximum In..."
...Note that a smaller Pr [30] improves capacitance matching (CFE ∝ Pr)....
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03 Aug 2017
TL;DR: In this article, the impact of the thickness of the ferroelectric (FE) layer of the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature.
Abstract: Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( $T_{\textsf {FE}})$ is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of $T_{\textsf {FE}}$ on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing $T_{\textsf {FE}}$ yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as $T_{\textsf {FE}}$ is increased. Depending on the attributes of the underlying transistor, increasing $T_{\textsf {FE}}$ beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of $T_{\textsf {FE}}$ on the circuit energy–delay. Our analysis shows that for high $T_{\textsf {FE}}$ , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay.
18 citations
TL;DR: In this paper, the analytical modeling of threshold voltage of an ultra-thin nanotube junctionless double-gate-all-around (NJL-DGAA) metal-oxide-semiconductor field effect transistor (MOSFET) was presented.
18 citations
References
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TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Abstract: It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.
1,722 citations
"NCFET Design Considering Maximum In..." refers background or methods in this paper
...The fe-layer can be modeled using the L-K equation as [1]...
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...They can provide the substantial improvement in on-current (Ion), off-current (Iof f ) [1]–[7] along with sub-threshold swing (SS)....
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TL;DR: A comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model is constructed and it is demonstrated how to solve the reaction-diffusion equations in a way that emphasizes the physical aspects of the degradation process and allows easy generalization of the existing work.
710 citations
TL;DR: In this article, structural and electrical evidence for a ferroelectric phase in yttrium doped hafnium oxide thin films is presented, based on X-ray diffraction.
Abstract: Structural and electrical evidence for a ferroelectric phase in yttrium doped hafnium oxide thin films is presented. A doping series ranging from 2.3 to 12.3 mol% YO1.5 in HfO2 was deposited by a thermal atomic layer deposition process. Grazing incidence X-ray diffraction of the 10 nm thick films revealed an orthorhombic phase close to the stability region of the cubic phase. The potential ferroelectricity of this orthorhombic phase was confirmed by polarization hysteresis measurements on titanium nitride based metal-insulator-metal capacitors. For 5.2 mol% YO1.5 admixture the remanent polarization peaked at 24 μC/cm2 with a coercive field of about 1.2 MV/cm. Considering the availability of conformal deposition processes and CMOS-compatibility, ferroelectric Y:HfO2 implies high scaling potential for future, ferroelectric memories.
499 citations
01 Dec 1987
TL;DR: In this article, the gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage, due to the band-to-band tunneling occurring in the deep-depletion layer in the gateto-drain overlap region.
Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.
338 citations
TL;DR: In this paper, a thermochemical description of the ultimate breakdown strength of high-k dielectrics suggests that E/sub bd/ should reduce approximately as (k)/sup -1/2/ over a wide range of dielectric materials while the field-acceleration parameter /spl gamma/ should increase in similar but inverse manner.
Abstract: The ultimate breakdown strength E/sub bd/ of a dielectric material is found to decrease as the dielectric-constant k increases. A thermochemical description of the ultimate breakdown strength of high-k dielectrics suggests that E/sub bd/ should reduce approximately as (k)/sup -1/2/ over a wide range of dielectric materials while the field-acceleration parameter /spl gamma/ should increase in similar but inverse manner. New time-dependent dielectric breakdown (TDDB) data are presented over a wide range of dielectric materials and E/sub bd/ was found to decrease as (k)/sup -0.65/ while /spl gamma/ increases as (k)/sup 0.66/. The good agreement between thermochemical theory and high-k TDDB observations suggests that the very high local electric field (Lorentz-relation/Mossotti-field) in high-k dielectrics tends to distort/weaken the polar molecular bonds making them more susceptible to bond breakage by standard Boltzmann processes and/or by hole-capture and thus lowers the breakdown strength.
307 citations