NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
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1,197 citations
Cites background from "NDC: Analyzing the impact of 3D-sta..."
...Recent efforts [2], [3], [4], [5], [58] decouple logic and memory designs in different dies, adopting 3D stacked memories with a logic layer that encapsulates processing units to perform computation, as shown in Figure 3(b)....
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...Also, while previous work focused on database and graph processing applications [3], [5], PRIME aims at accelerating NN applications....
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...introduce promising solutions to the challenges [2], [3], [4], [5], by leveraging 3D memory technologies [6] to integrate computation logic with the memory....
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References
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"NDC: Analyzing the impact of 3D-sta..." refers background in this paper
...This paper focuses on in-memory MapReduce workloads that are commercially important and are especially suitable for NDC because of their embarrassing parallelism and largely localized memory accesses....
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1,058 citations
"NDC: Analyzing the impact of 3D-sta..." refers methods in this paper
...Phoenix [53] is a programming API and runtime that implements MapReduce for shared-memory systems....
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793 citations
"NDC: Analyzing the impact of 3D-sta..." refers background in this paper
...The Mars framework does the same for GPUs [33]....
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679 citations
"NDC: Analyzing the impact of 3D-sta..." refers methods in this paper
...Loh [44] describes various design strategies if the memory chips were t o be used as main memory....
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