Proceedings ArticleDOI
Near speed-of-light on-chip interconnects using pulsed current-mode signalling
Jose Anup P,G. Patounakis,Kenneth L. Shepard +2 more
- pp 108-111
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TLDR
Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion.Abstract:
In this paper, we describe the design of on-chip repeaterless interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8 Gbps serial link employing this pulsed current-mode signalling in a 0.18 /spl mu/m CMOS process is described and measured.read more
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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
TL;DR: This paper provides a general description of NoC architectures and applications and enumerates several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation.
Proceedings ArticleDOI
Flattened Butterfly Topology for On-Chip Networks
TL;DR: This work proposes the use of high-radix networks in on-chip interconnection networks and describes how the flattened butterfly topology can be mapped to on- chip networks and shows that the flattened Butterfly can increase throughput by up to 50% compared to a concentrated mesh and reduce latency by 28% while reducing the power consumption by 38%Compared to a mesh network.
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On-Chip Networks
TL;DR: Various fundamental aspects of on-chip network design are examined and the reader is provided with an overview of the current state-of-the-art research in this field.
Journal ArticleDOI
Flattened Butterfly Topology for On-Chip Networks
TL;DR: This work proposes the use of high-radix networks in on-chip networks and describes how the flattened butterfly topology can be mapped to on- chip networks and offers lower latency and energy consumption than conventional on-Chip topologies.
References
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Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Journal ArticleDOI
The future of wires
R. Ho,Ken Mai,Mark Horowitz +2 more
TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Book
Digital and analog communication systems
TL;DR: This book provides a broad introduction to basic analog and digital principles and their application to the design and analysis of real- world communication systems and provides readers with a working knowledge of how to use both classical mathematical and personal computer methods to analyze, design, and simulate modern communication systems.
Journal ArticleDOI
Low-jitter and process independent DLL and PLL based on self biased techniques
TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.