New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy
05 Jul 2005-IEEE Transactions on Circuits and Systems I-regular Papers (IEEE)-Vol. 52, Iss: 5, pp 911-919
TL;DR: A new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy that can reduce hardware complexity and computation cycles compared with existing FFT processors is proposed.
Abstract: The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.
Citations
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TL;DR: A fault diagnosis strategy based on the principle component analysis and the multiclass relevance vector machine (PCA-mRVM) that not only achieves higher model sparsity and shorter diagnosis time, but also provides probabilistic outputs for every class membership.
Abstract: Multilevel inverters, for their distinctive performance, have been widely used in high voltage and high-power applications in recent years. As power electronics equipment reliability is very important and to ensure multilevel inverter systems stable operation, it is important to detect and locate faults as quickly as possible. In this context and to improve fault diagnosis accuracy and efficiency of a cascaded H-bridge multilevel inverter system (CHMLIS), a fault diagnosis strategy based on the principle component analysis and the multiclass relevance vector machine (PCA-mRVM), is elaborated and proposed in this paper. First, CHMLIS output voltage signals are selected as input fault classification characteristic signals. Then, a fast Fourier transform is used to preprocess these signals. PCA is used to extract fault signals features and to reduce samples dimensions. Finally, an mRVM model is used to classify faulty samples. Compared to traditional approaches, the proposed PCA-mRVM strategy not only achieves higher model sparsity and shorter diagnosis time, but also provides probabilistic outputs for every class membership. Experimental tests are carried out to highlight the proposed PCA-mRVM diagnosis performances.
181 citations
Cites methods from "New continuous-flow mixed-radix (CF..."
...First, to make the fault signature obvious, the fast Fourier transform (FFT) of the sampled data is computed in order to extract the frequency domain of the signals [31], [32]....
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TL;DR: An multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length is presented.
Abstract: This paper presents an multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length. Based on the MDC architecture, we propose to use radix-Ns butterflies at each stage, where Ns is the number of data streams, so that there is only one butterfly needed in each stage. Consequently, a 100% utilization rate in computational elements is achieved. Moreover, thanks to the simple control mechanism of the MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. Since the memory requirements usually dominate the die area of FFT/inverse fast Fourier transform (IFFT) processors, the proposed scheme can effectively reduce the memory size and thus the die area as well. Furthermore, to apply the proposed scheme in practical applications, we let Ns=4 and implement a 4-stream FFT/IFFT processor with variable length including 2048, 1024, 512, and 128 for MIMO-OFDM systems. This processor can be used in IEEE 802.16 WiMAX and 3GPP long term evolution applications. The processor was implemented with an UMC 90-nm CMOS technology with a core area of 3.1 mm2. The power consumption at 40 MHz was 63.72/62.92/57.51/51.69 mW for 2048/1024/512/128-FFT, respectively in the post-layout simulation. Finally, we analyze the complexity and performance of the implemented processor and compare it with other processors. The results show advantages of the proposed scheme in terms of area and power consumption.
99 citations
Cites background from "New continuous-flow mixed-radix (CF..."
...Continuous-flow mixedradix (CFMR) FFT [8], [9] utilizes two N-sample memories to generate a continuous output stream....
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TL;DR: A generalized mixed-radix (GMR) algorithm is proposed for memory-based fast Fourier transform (FFT) processors to support prime-sized and traditional 2n -point FFTs simultaneously and transforms the index to a multidimensional vector for efficient computation.
Abstract: In this brief, a generalized mixed-radix (GMR) algorithm is proposed for memory-based fast Fourier transform (FFT) processors to support prime-sized and traditional 2n -point FFTs simultaneously It transforms the index to a multidimensional vector for efficient computation By controlling the index vector to satisfy the ?vector reverse? behavior, the GMR algorithm can support not only in-place policy for both computation and I/O data for continuous data flow to minimize the memory size but also multibank memory structures to increase the maximum throughput without memory conflict Finally, a low-complexity implementation of an index vector generator is also proposed for our algorithm
81 citations
TL;DR: A generalized conflict-free memory addressing scheme for memory-based fast Fourier transform (FFT) processors with parallel arithmetic processing units made up of radix-2q multi-path delay commutator (MDC) is presented.
Abstract: This paper presents a generalized conflict-free memory addressing scheme for memory-based fast Fourier transform (FFT) processors with parallel arithmetic processing units made up of radix-2q multi-path delay commutator (MDC). The proposed addressing scheme considers the continuous-flow operation with minimum shared memory requirements. To improve throughput, parallel high-radix processing units are employed. We prove that the solution to non-conflict memory access satisfying the constraints of the continuous-flow, variable-size, higher-radix, and parallel-processing operations indeed exists. In addition, a rescheduling technique for twiddle-factor multiplication is developed to reduce hardware complexity and to enhance hardware efficiency. From the results, we can see that the proposed processor has high utilization and efficiency to support flexible configurability for various FFT sizes with fewer computation cycles than the conventional radix-2/radix-4 memory-based FFT processors.
70 citations
Cites background or methods from "New continuous-flow mixed-radix (CF..."
...1, it supports the continuous-flow operation and merges the input and output buffer so as to minimize the total memory requirement to as in [9] and [10]....
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...However, it has been shown in [9] and [10] that a continuous-flow FFT processor can minimize the storage to...
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...In the past, numerous FFT processors have been designed [2]–[9]....
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...In [9] and [11], an in-place strategy was applied for the radix-2/4 butterfly unit....
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...Among them, pipelined single-path delay feedback (SDF) architecture [3]–[6] and memory-based/cache-memorybased architecture [7]–[9] are two popular solutions....
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TL;DR: This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph.
Abstract: This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.
56 citations
Cites background from "New continuous-flow mixed-radix (CF..."
...Moreover, when compared to the in-place complex FFT [5], [6], one obvious advantage of our proposed RFFT architecture is that the length of the required memory can be reduced by a factor of 2....
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References
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TL;DR: This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.
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319 citations
"New continuous-flow mixed-radix (CF..." refers background or methods or result in this paper
...The existing processors [21], [22] requires one -word memory since they use the in-place strategy [20]; however, they cannot support the CF FFT. Spiffee [21] using the in-place strategy requires many computation cycles since they use the radix-2 algorithm....
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243 citations
"New continuous-flow mixed-radix (CF..." refers methods in this paper
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TL;DR: In this paper, a multibank address assignment for an arbitrary fixed radix fast Fourier transform (FFT) algorithm suitable for high-speed single-chip implementation is developed, which is memory-bank conflict-free to allow simultaneous access to all the data needed for calculation of each of the radix r butterflies as they occur in the algorithm.
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131 citations
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TL;DR: This article discusses the VLSI implications of high-speed coded orthogonal frequency-division multiplexing modulation by looking at practical examples of the computational blocks that constitute a COFDM modem and then examining examples ofCOFDM chips.
Abstract: This article discusses the VLSI implications of high-speed coded orthogonal frequency-division multiplexing modulation. This is achieved by looking at practical examples of the computational blocks that constitute a COFDM modem and then examining examples of COFDM chips.
77 citations
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20 Oct 1999
TL;DR: This work discusses the design and implementation of a high-speed, low power 1024-point pipeline FFT processor, which is efficient in terms of power consumption and chip area.
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65 citations
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