New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise
18 May 2008-pp 232-235
TL;DR: A new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus and shows that the overall linearity can be significantly improved using this technique.
Abstract: This paper describes a new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This low- amplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then used to calculate the required calibrating-codes. As an example, the calibration of a 13-bit pipeline ADC shows that the overall linearity can be significantly improved using this technique.
Citations
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TL;DR: This paper proposes a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs, and demonstrates that it can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management.
Abstract: Solutions to the integration challenges of a new thermal sensor technology into 3-D integrated circuits (ICs) will be discussed in this paper Our proposed architecture uses bimetallic thin-film thermocouples, which are thermally linked to points of measurement throughout the 3-D stack with dedicated vias These vias will be similar to thermal through-silicon vias (TSVs) in structure, yet different in functionality We propose a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs A fraction of thermal TSV resources is decoupled from their original use and repurposed for the temperature sensing infrastructure Tradeoffs concerning the reduction of the thermal TSV resources are investigated Furthermore, we present an end-to-end system, including the physical realization of the sensor network as well as its analog interface circuitry with the sensor data sampling unit We demonstrate the operation and correctness of this interface with transistor-level simulations Next, through thermal modeling and simulation using a state-of-the-art tool (FloTHERM), we demonstrate that we can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management (conforming to a peak temperature constraint of 95 °C)
7 citations
Cites methods from "New simple digital self-calibration..."
...The built-in selfcalibration techniques [29], [30] for on-chip ADC can be used to compensate for process variations....
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01 Nov 2014
TL;DR: The proposed ADC BIST system is based in a uniform histogram approach to test the linearity of ADCs and shows that the error on the maximum INL is 0.13 LSB for the Mersenne twister pseudorandom uniform noise generator.
Abstract: This paper describes a digital built-in-self-test (BIST) solution to ADC dynamic performance testing. The proposed ADC BIST system is based in a uniform histogram approach to test the linearity of ADCs. A pipeline ADC with a resolution of 10 bits, a DAC with the same resolution as the ADC under test and the proposed BIST scheme were modeled and simulated in MATLAB to prove its validity. Several 32 bits pseudorandom uniform noise generators were evaluated. When compared with the Gaussian histogram approach, the obtained results show that the error on the maximum INL is 0.13 LSB for the Mersenne twister pseudorandom uniform noise generator and an adequate statistical significance is obtained with a quarter of the samples. Additionally, the number and complexity of the circuits are reduced.
5 citations
Cites methods from "New simple digital self-calibration..."
...Other techniques for generating noise use the internal thermal noise of the ADC [24] or the sum of a uniformly distributed noise sequence with a variable DC source [25]....
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18 Dec 2014
TL;DR: This work characterises the distorting process and linearises the system in real-time using statistical measurements of the observed noise at the output of a cascaded system of amplifiers.
Abstract: It is well-known that in a cascaded system of amplifiers the majority of noise is due to the first stage and the majority of distortion due to the final stage. Consequently, the observed noise at the output is subject to the same nonlinear process as the signal of interest. We use this fact to characterise the distorting process and linearise the system in real-time using statistical measurements of this noise.
2 citations
Cites background from "New simple digital self-calibration..."
...Figueiredo, et al. [8] proposed the use of internal noise in pipelined ADCs to produce a uniformly-distributed test signal for the purpose of histogramming....
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13 Jul 2016
TL;DR: A new technique for compensation of static nonlinear distortion using the internal noise of the device improves upon previous approaches by allowing highly-efficient fixed-point implementation, and represents the first step towards direct integration with analog hardware in order to produce an ADC that is blind to its analog frontend.
Abstract: In most designs, residual nonlinearity is considered an inescapable curse-even when it is known to be present, it is often assumed to be too unpredictable or unstable to be dealt with in postprocessing. However, with the aid of outputonly system identification, this is no longer the case. We have developed a new technique for compensation of static nonlinear distortion using the internal noise of the device. It improves upon previous approaches by allowing highly-efficient fixed-point implementation, and represents the first step towards direct integration with analog hardware in order to produce an ADC that is blind to its analog frontend.
1 citations
Cites methods from "New simple digital self-calibration..."
...Another attempt [9] used modifications to the inputoutput configuration of a pipelined ADC in order to produce uniformly distributed noise—however, this comes with the disadvantage of requiring that the ADC be disconnected from the circuit....
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TL;DR: In this article, a switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed, which is based on associating two sets of two capacitors in cross series during the amplification phase.
Abstract: A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed. This structure is based on associating two sets of two capacitors in cross series during the amplification phase. This circuit permits the common-mode voltage of the sample signal to reach full swing. Using the charge-complement technique, the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively. Simulation results show that as sample signal common-mode voltage changes, the difference between the minimum and maximum gain error is less than 0.03%. When the capacitor mismatch is increased from 0 to 0.2%, the gain error is deteriorated by 0.00015%. In all simulations, the gain of amplifier is 69 dB.
1 citations
References
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01 Dec 1993
TL;DR: In this paper, a 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented with a radix 1.93, 1 b per stage design, which accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain and capacitor nonlinearity contributing to DNL.
Abstract: A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. >
441 citations
TL;DR: A self-calibrated pipelined A/D converter technique potentially appropriate for high-resolution video applications that requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques.
Abstract: Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3- mu m CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil/sup 2/ (26 mm/sup 2/), with a single 5-V supply and two-phase nonoverlapping clock. >
244 citations
"New simple digital self-calibration..." refers methods in this paper
...Analogue techniques require calibration DACs and precision analogue components [1, 2]....
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TL;DR: A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs).
Abstract: A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >
219 citations
TL;DR: In this paper, a multibit, rather than single-bit resolution per-stage architectures have been considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks.
Abstract: High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.
77 citations
06 Jul 1998
TL;DR: A broadband variant of the histogram test where Gaussian noise is used as a stimulus signal is presented and tolerance and confidence intervals are determined both for the integral nonlinearity (INL) and differential non linearity (DNL) vectors, related to the number of samples acquired.
Abstract: A broadband variant of the histogram test where Gaussian noise is used as a stimulus signal is presented. A methodology allowing for an automated and extensive characterization of analog-to-digital converters (ADCs) is given. Tolerance and confidence intervals are determined both for the integral nonlinearity (INL) and differential nonlinearity (DNL) vectors, related to the number of samples acquired. Experimental results of the characterization of a VXI waveform digitizer using this methodology are shown.
51 citations
"New simple digital self-calibration..." refers methods in this paper
...There are several advantages when GN is used together with histogram-based calibration: the ADC can be seen as a “black-box” and does not need to be modified; GN, having a uniform power spectral density, allows full-speed dynamic calibration [8], and the use of a histogram eliminates uncertainties of the calibrating-codes due to noise....
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