New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise
18 May 2008-pp 232-235
TL;DR: A new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus and shows that the overall linearity can be significantly improved using this technique.
Abstract: This paper describes a new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This low- amplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then used to calculate the required calibrating-codes. As an example, the calibration of a 13-bit pipeline ADC shows that the overall linearity can be significantly improved using this technique.
Citations
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01 Dec 2014
TL;DR: This circuit combines three main techniques that lead to a simulated reduction of the power dissipation of the order of 4 times, when compared to the conventional 1.5-bit MDAC circuit, as all these innacuracies are cancelled thanks to the techniques employed.
Abstract: In this paper a novel and mismatch-insensitive 1.5-bit MDAC is proposed. This circuit combines three main techniques that lead to a simulated reduction of the power dissipation of the order of 4 times, when compared to the conventional 1.5-bit MDAC circuit. Simulations also have shown that the proposed 1.5-bit MDAC is capable of achieving an SNDR of around 74 dB, i.e. compatible with 12 bits, corresponding to a 25 dB (4 bits) improvement when compared to the classic 1.5-bit MDAC. It is worth noticing that these results are achieved with a low gain, poor linearity and noisy residue amplifier, as all these innacuracies are cancelled thanks to the techniques employed.
Cites background from "New simple digital self-calibration..."
...For these ADCs, the enhancing of energy and area efficiency is of the utmost importance (ex: mobile terminals) [1]....
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References
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01 Dec 1993
TL;DR: In this paper, a 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented with a radix 1.93, 1 b per stage design, which accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain and capacitor nonlinearity contributing to DNL.
Abstract: A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. >
441 citations
TL;DR: A self-calibrated pipelined A/D converter technique potentially appropriate for high-resolution video applications that requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques.
Abstract: Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3- mu m CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil/sup 2/ (26 mm/sup 2/), with a single 5-V supply and two-phase nonoverlapping clock. >
244 citations
"New simple digital self-calibration..." refers methods in this paper
...Analogue techniques require calibration DACs and precision analogue components [1, 2]....
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TL;DR: A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs).
Abstract: A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >
219 citations
TL;DR: In this paper, a multibit, rather than single-bit resolution per-stage architectures have been considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks.
Abstract: High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.
77 citations
06 Jul 1998
TL;DR: A broadband variant of the histogram test where Gaussian noise is used as a stimulus signal is presented and tolerance and confidence intervals are determined both for the integral nonlinearity (INL) and differential non linearity (DNL) vectors, related to the number of samples acquired.
Abstract: A broadband variant of the histogram test where Gaussian noise is used as a stimulus signal is presented. A methodology allowing for an automated and extensive characterization of analog-to-digital converters (ADCs) is given. Tolerance and confidence intervals are determined both for the integral nonlinearity (INL) and differential nonlinearity (DNL) vectors, related to the number of samples acquired. Experimental results of the characterization of a VXI waveform digitizer using this methodology are shown.
51 citations
"New simple digital self-calibration..." refers methods in this paper
...There are several advantages when GN is used together with histogram-based calibration: the ADC can be seen as a “black-box” and does not need to be modified; GN, having a uniform power spectral density, allows full-speed dynamic calibration [8], and the use of a histogram eliminates uncertainties of the calibrating-codes due to noise....
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