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Proceedings ArticleDOI

New simple digital self-calibration technique for pipeline ADCs using the internal thermal noise

TL;DR: A new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus and shows that the overall linearity can be significantly improved using this technique.
Abstract: This paper describes a new digital-domain self- calibration technique for high-speed pipeline A/D converters using the internal thermal noise as input stimulus. This low- amplitude noise is amplified and recycled by the ADC itself and, due to the successive foldings, it is naturally converted into uniform noise. This noise is then used to calculate the required calibrating-codes. As an example, the calibration of a 13-bit pipeline ADC shows that the overall linearity can be significantly improved using this technique.

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Citations
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Journal ArticleDOI
TL;DR: This paper proposes a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs, and demonstrates that it can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management.
Abstract: Solutions to the integration challenges of a new thermal sensor technology into 3-D integrated circuits (ICs) will be discussed in this paper Our proposed architecture uses bimetallic thin-film thermocouples, which are thermally linked to points of measurement throughout the 3-D stack with dedicated vias These vias will be similar to thermal through-silicon vias (TSVs) in structure, yet different in functionality We propose a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs A fraction of thermal TSV resources is decoupled from their original use and repurposed for the temperature sensing infrastructure Tradeoffs concerning the reduction of the thermal TSV resources are investigated Furthermore, we present an end-to-end system, including the physical realization of the sensor network as well as its analog interface circuitry with the sensor data sampling unit We demonstrate the operation and correctness of this interface with transistor-level simulations Next, through thermal modeling and simulation using a state-of-the-art tool (FloTHERM), we demonstrate that we can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management (conforming to a peak temperature constraint of 95 °C)

7 citations


Cites methods from "New simple digital self-calibration..."

  • ...The built-in selfcalibration techniques [29], [30] for on-chip ADC can be used to compensate for process variations....

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Proceedings ArticleDOI
01 Nov 2014
TL;DR: The proposed ADC BIST system is based in a uniform histogram approach to test the linearity of ADCs and shows that the error on the maximum INL is 0.13 LSB for the Mersenne twister pseudorandom uniform noise generator.
Abstract: This paper describes a digital built-in-self-test (BIST) solution to ADC dynamic performance testing. The proposed ADC BIST system is based in a uniform histogram approach to test the linearity of ADCs. A pipeline ADC with a resolution of 10 bits, a DAC with the same resolution as the ADC under test and the proposed BIST scheme were modeled and simulated in MATLAB to prove its validity. Several 32 bits pseudorandom uniform noise generators were evaluated. When compared with the Gaussian histogram approach, the obtained results show that the error on the maximum INL is 0.13 LSB for the Mersenne twister pseudorandom uniform noise generator and an adequate statistical significance is obtained with a quarter of the samples. Additionally, the number and complexity of the circuits are reduced.

5 citations


Cites methods from "New simple digital self-calibration..."

  • ...Other techniques for generating noise use the internal thermal noise of the ADC [24] or the sum of a uniformly distributed noise sequence with a variable DC source [25]....

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Proceedings ArticleDOI
18 Dec 2014
TL;DR: This work characterises the distorting process and linearises the system in real-time using statistical measurements of the observed noise at the output of a cascaded system of amplifiers.
Abstract: It is well-known that in a cascaded system of amplifiers the majority of noise is due to the first stage and the majority of distortion due to the final stage. Consequently, the observed noise at the output is subject to the same nonlinear process as the signal of interest. We use this fact to characterise the distorting process and linearise the system in real-time using statistical measurements of this noise.

2 citations


Cites background from "New simple digital self-calibration..."

  • ...Figueiredo, et al. [8] proposed the use of internal noise in pipelined ADCs to produce a uniformly-distributed test signal for the purpose of histogramming....

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Proceedings ArticleDOI
13 Jul 2016
TL;DR: A new technique for compensation of static nonlinear distortion using the internal noise of the device improves upon previous approaches by allowing highly-efficient fixed-point implementation, and represents the first step towards direct integration with analog hardware in order to produce an ADC that is blind to its analog frontend.
Abstract: In most designs, residual nonlinearity is considered an inescapable curse-even when it is known to be present, it is often assumed to be too unpredictable or unstable to be dealt with in postprocessing. However, with the aid of outputonly system identification, this is no longer the case. We have developed a new technique for compensation of static nonlinear distortion using the internal noise of the device. It improves upon previous approaches by allowing highly-efficient fixed-point implementation, and represents the first step towards direct integration with analog hardware in order to produce an ADC that is blind to its analog frontend.

1 citations


Cites methods from "New simple digital self-calibration..."

  • ...Another attempt [9] used modifications to the inputoutput configuration of a pipelined ADC in order to produce uniformly distributed noise—however, this comes with the disadvantage of requiring that the ADC be disconnected from the circuit....

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Journal ArticleDOI
TL;DR: In this article, a switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed, which is based on associating two sets of two capacitors in cross series during the amplification phase.
Abstract: A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed. This structure is based on associating two sets of two capacitors in cross series during the amplification phase. This circuit permits the common-mode voltage of the sample signal to reach full swing. Using the charge-complement technique, the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively. Simulation results show that as sample signal common-mode voltage changes, the difference between the minimum and maximum gain error is less than 0.03%. When the capacitor mismatch is increased from 0 to 0.2%, the gain error is deteriorated by 0.00015%. In all simulations, the gain of amplifier is 69 dB.

1 citations

References
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Journal ArticleDOI
TL;DR: A digital-domain self-calibration technique for video-rate pipeline A/D converters based on a Gaussian white noise input signal is presented and a design example is shown to illustrate that the overall linearity of a pipeline ADC can be highly improved using this technique.
Abstract: A digital-domain self-calibration technique for video-rate pipeline A/D converters based on a Gaussian white noise input signal is presented. The proposed algorithm is simple and efficient. A design example is shown to illustrate that the overall linearity of a pipeline ADC can be highly improved using this technique.

12 citations


"New simple digital self-calibration..." refers background or methods in this paper

  • ...The research work was supported by the Portuguese Foundation for Science and Technology (FCT/MCT) under LEADER (PTDC/EEA-ELC/69791/2006) and SIPHASE (POSC/EEA-ESSE/ 61863/2004) Projects....

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  • ...1(a) and conceptually described in [6, 7], consists of applying a Gaussian noise (GN) stimulus to the input of the ADC and calculating the calibration-codes from the histogram of the output codes....

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  • ...The authors would like to thank Prof. M. Medeiros Silva for the many suggestions that substantially improved the quality of this paper....

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Proceedings Article
01 Jan 2000
TL;DR: In this article, a low-power 14-b 5 MS/s area-optimized pipelined ADC with background analog self-calibration is presented, where the core area is 10mm2 and dissipates less than 145mW at 5V.
Abstract: This paper presents a low-power 14-b 5 MS/s area-optimized pipelined ADC with background analog self-calibration. Measured results from the prototypes fabricated in a 0.6 µm 5 V DPDM CMOS technology show 13.5-b DNL, 12-b INL, 80 dB SFDR and 76 dB SNDR. The core area is 10mm2and it dissipates less than 145mW at 5V.

9 citations


"New simple digital self-calibration..." refers methods in this paper

  • ...Analogue techniques require calibration DACs and precision analogue components [1, 2]....

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Proceedings ArticleDOI
25 May 2003
TL;DR: An application design example of the self-calibration of a 12b, 40 MS/s CMOS pipeline ADC is shown to illustrate that the overall linearity of the ADC can be highly improved using this technique.
Abstract: A digital-domain self-calibration technique for video-rate pipeline A/D converters based on a white Gaussian noise input signal is presented. The implementation of the proposed algorithm requires simple digital circuitry. An application design example of the self-calibration of a 12b, 40 MS/s CMOS pipeline ADC is shown to illustrate that the overall linearity of the ADC can be highly improved using this technique.

3 citations


"New simple digital self-calibration..." refers background or methods in this paper

  • ...However, there are three drawbacks in the technique described in [6, 7]: 1) it requires two additional analogue blocks, namely a GN generator (GNG) and a programmablegain amplifier (PGA) to adjust the standard-deviation (σ) of the GNG; 2) since the output histogram has a Gaussian shape, an internal table containing the ideal mathematically-produced histogram has to be stored in a memory; 3) the σ of the GNG has to be calibrated with reasonable accuracy before the calibration of the ADC itself....

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  • ...(a) Technique in [6, 7]; (b) Proposed new technique without Gaussian noise generator and PGA....

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  • ...1(a) and conceptually described in [6, 7], consists of applying a Gaussian noise (GN) stimulus to the input of the ADC and calculating the calibration-codes from the histogram of the output codes....

    [...]