Nickel silicide metal gate FDSOI devices with improved gate oxide leakage
08 Dec 2002-pp 271-274
TL;DR: In this article, the authors demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices and show capacitance equivalent gate oxide thickness (CET) 06 nm thinner than poly gates.
Abstract: Fully depleted SOI (FDSOI) devices with undoped channel require metal gates to achieve correct threshold voltages We demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices Metal gates are stable on 2 nm gate oxide and show capacitance equivalent gate oxide thickness (CET) 06 nm thinner than poly gates The gate leakage current is up to two orders of magnitude lower and high mobility is achieved (peak electron mobility 670 cm/sup 2//Vs and 170 cm/sup 2//Vs for holes)
Citations
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TL;DR: The paper addresses stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates in mainstream Si CMOS technology.
Abstract: The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-κ dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.
269 citations
01 Dec 2004
TL;DR: A new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications and a 6-transistor SRAM memory cell in which even more benefit is obtained from the new device structure by adding a feedback mechanism is proposed.
Abstract: We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal gates and ion implantation for V/sub th/ control. The target V/sub th/ for low-power applications was achieved by using ion implantation for V/sub th/ control. We propose a 6-transistor SRAM memory cell in which we obtain even more benefit from the new device structure by adding a feedback mechanism. A proposed 6-Tr SRAM memory cell is shown to dramatically improve SNM characteristics at the 65-nm technology nodes, and this effect will also apply at finer nodes.
175 citations
TL;DR: In this article, the authors reviewed various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.
Abstract: High-k dielectrics have been intensively investigated during the last decade, and their performance as a gate dielectric has been improved to the level of conventional SiO2-based gate dielectric at an equivalent oxide thickness (EOT) ~1 nm. The understanding on metal electrodes and their interaction with the underlying high-k dielectric has been expanded, and various CMOS device results with metal electrode/high-k gate dielectric stacks have been reported, indicating the maturity of this technology. The next challenges lie in scaling the gate stack to 0.5-nm EOT to extend the usage of the metal electrode/high-k gate dielectric stacks to future technology generations. A new class of high-k dielectric that has a dielectric constant higher than 26 and a barrier height of ~5.0 eV and above will be needed to achieve this target. Recent progress in this so-called higher k dielectric research is summarized, and its benefit to the gate leakage current is discussed. This paper also reviews various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.
65 citations
Cites methods from "Nickel silicide metal gate FDSOI de..."
...The first FUSI gate MOSFET was demonstrated using CoSi2 in 2001 [34] and NiSi in 2002 [35]....
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IBM1
TL;DR: In this paper, the NiSi-gate work function control was demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV.
Abstract: Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors. NiSi-gate workfunction control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi/sub 2/. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance.
64 citations
IBM1
TL;DR: In this article, the effect of various impurities including B, P, As, Sb, In, and Al on the work function of NiSi gates was investigated. But, the effect on gate capacitance, mobility, local work function stability, and adhesion was not studied.
Abstract: Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.
54 citations
References
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TL;DR: In this paper, low resistivity Ru and Ru-Ta alloy films, deposited via reactive sputtering, were evaluated as gate electrodes for p- and n-MOSFET devices, respectively.
Abstract: In this letter, low resistivity Ru and Ru-Ta alloy films, deposited via reactive sputtering, were evaluated as gate electrodes for p- and n-MOSFET devices, respectively. MOSFETs fabricated via a conventional process flow indicated that the work functions of Ru and Ru-Ta alloys were compatible with p- and n-MOSFET devices, respectively. Both of the metal gated devices eliminated gate depletion effects. Good MOSFET characteristics, such as I/sub DS/-V/sub GS/ and mobility, were obtained for both Ru-gated PMOSFETs and Ru-Ta gated NMOSFETs.
81 citations
TL;DR: In this article, the inversion-layer mobility in n-channel Si MOSFETs fabricated on a silicon-on-insulator (SOI) substrate was investigated.
Abstract: This paper reports on a study of the inversion-layer mobility in n-channel Si MOSFETs fabricated on a silicon-on-insulator (SOI) substrate. In order to make clear the influences of the buried-oxide interface on the inversion-layer mobility in ultra-thin film SOI transistors, SOI wafers of different quality at the buried-oxide interface were prepared, and the mobility behaviors were compared quantitatively. The transistors with a relatively thick SOI film exhibited the universal relationship between the effective mobility and the effective normal field, regardless of the buried-oxide interface quality. It was found, however, that Coulomb scattering due to charged centers at the backside interface between SOI films and buried oxides has great influence on the effective mobility in the thin SOI thickness region, depending on the buried-oxide interface quality. This means that Coulomb scattering due to charged centers at the buried-oxide interface can degrade the mobility with decreasing SOI thickness, unless the SOI wafer quality at the buried-oxide interface is controlled carefully.
77 citations