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Proceedings ArticleDOI

Non-Blocking Concurrent FIFO Queues with Single Word Synchronization Primitives

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TLDR
2 efficient and practical non-blocking implementations of a concurrent array-based FIFO queue that are suitable for both multiprocessor as well as preemptive multithreaded systems are presented.
Abstract
We present 2 efficient and practical non-blocking implementations of a concurrent array-based FIFO queue that are suitable for both multiprocessor as well as preemptive multithreaded systems. It is well known that concurrent FIFO queues relying on mutual exclusion cause blocking, which have several drawbacks and degrade overall system performance. Link-based non-blocking queue algorithms have a memory management problem whereby a removed node from the queue can neither be freed nor reused because other threads may still be accessing the node. Existing solutions to this problem introduce a fair amount of overhead and, when the number of threads that can access the FIFO queue is moderate to high, are shown to be less efficient compared to array-based algorithms, which inherently do not suffer from this problem. In addition to being independent on advance knowledge of the number of threads that can access the queue, our new algorithms improve on previously proposed algorithms in that they do not require any special instruction other than a load-linked/store-conditional or a compare-and-swap atomic instruction both operating on pointer-wide number of bits. Our new algorithms are thus portable to a broader range of architectures.

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Citations
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Dissertation

Multiprocessor-safe wait-free queue in RTSJ

TL;DR: A novel algorithm for concurrently accessing shared data structures in a shared memory multi-processor (or multi-core) systems is implemented as an arraybased First-In-First-Out (FIFO) queue, which improves the scalability and time predictability in multi-threaded applications.
Book ChapterDOI

A Parallel Full-System Emulator for Risc Architure Host

TL;DR: This paper port a parallel full-system emulator to RISC host to achieve higher performance by utilize all the multi-core resources from physical CPU, in contrast the traditional full- system emulator is sequentially in SMP emulation and can only use one core of host machine.
Proceedings ArticleDOI

A Practical Non-blocking Route Propagation Technology for Threaded BGP

TL;DR: A non-blocking technology to accelerate the route propagation in TBGP (Threaded BGP), which eliminates various contentions effectively, achieves con-current queue operations by SCLF lock-free algorithm, and also avoids the performance penalty by cache line thrashing.
Journal ArticleDOI

A Family of Relaxed Concurrent Queues for Low-Latency Operations and Item Transfers

TL;DR: The Relaxed Concurrent Queues algorithm is a provably linearizable lock-free member of the RCQ family and it is experimentally show that RCQS achieves factors to orders of magnitude advantage over the state-of-the-art strict or relaxed queue algorithms across several latency and throughput statistics of the queue operations and item transfers.
Proceedings ArticleDOI

Value Iteration on Multicore Processors

TL;DR: In this paper, the authors explore strategies to run the sate-of-the-art cache efficient algorithm for value iteration on a multicore processor, and demonstrate a speedup of up to 2.59 on a 10-core multiprocessor using 20 threads on popular benchmark data.
References
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Journal ArticleDOI

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TL;DR: This paper defines linearizability, compares it to other correctness conditions, presents and demonstrates a method for proving the correctness of implementations, and shows how to reason about concurrent objects, given they are linearizable.
Journal ArticleDOI

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Proceedings ArticleDOI

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Journal ArticleDOI

Nonblocking Algorithms and Preemption-Safe Locking on Multiprogrammed Shared Memory Multiprocessors

TL;DR: The results indicate that the nonblocking queue consistently outperforms the best known alternatives and that data-structure-specific nonblocking algorithms, which exist for queues, stacks, and counters, can work extremely well.
Proceedings ArticleDOI

Practical implementations of non-blocking synchronization primitives

TL;DR: The results presented here eliminate the problem by providing practical means for implementing any algorithm that is based on these instructions on any multiprocessor that provides either CAS or a form of LL and SC that is sufficiently weak that it is provided by all current hardware implementations of these instructions.