Non-oxidized porous silicon-based power AC switch peripheries
TL;DR: It seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles.
Abstract: We present in this paper a novel application of porous silicon (PS) for low-power alternating current (AC) switches such as triode alternating current devices (TRIACs) frequently used to control small appliances (fridge, vacuum cleaner, washing machine, coffee makers, etc.). More precisely, it seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device. Based on the technological aspects of the most commonly used AC switch peripheries physically responsible of the TRIAC blocking performances (leakage current and breakdown voltage), we suggest to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles. Then, we comment the voltage capability of practical samples emanating from the proposed architecture. Thanks to the characterization results of simple Al-PS-Si(P) structures, the experimental observations are interpreted, thus opening new outlooks in the field of AC switch peripheries.
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TL;DR: In this article, the authors present all the possible porous silicon substrates, which can be used for RF devices, and the intrinsic electrical properties of porous silicon such as AC electrical conductivity or dielectric constant are also detailed.
Abstract: The increasing expansion of telecommunication applications leads to the integration of complete system-on-chip associating analog and digital processing units. Besides, the passive elements occupy an increasing silicon footprint, compromising circuit scalability and cost. Moreover, passive components’ performances are limited by the proximity of lossy Si substrate and surrounding metallization. Then, obviously, the characteristics of the substrate become crucial for monolithic radio frequency (RF) systems to reach high performances. So, looking for integrated circuit compatible processes, porous silicon (PS) seems to be a promising candidate as it can provide localized isolating regions from various silicon substrates. In this review, we first present all the possible porous silicon substrates, which can be used for RF devices. In particular, we put the emphasis on the etching conditions, leading to high thickness localized PS layers. The intrinsic electrical properties of porous silicon such as AC electrical conductivity or dielectric constant are also detailed, and the results extracted from the literature are commented. Then, we describe the performances of widespread RF devices, that is, inductors or coplanar waveguides. Finally, we describe methodologies used for predicting RF electrical responses of PS isolated devices, based on electromagnetic simulations.
38 citations
TL;DR: In this paper, the porosity of porous silicon (PS) was found to be the major contributor to the PS resistivity (ρPS), and ρPS increases exponentially with P%.
Abstract: The resistivity of p type porous silicon (PS) is reported on a wide range of PS physical properties. Al/PS/Si/Al structures were used and a rigorous experimental protocol was followed. The PS porosity (P%) was found to be the major contributor to the PS resistivity (ρPS). ρPS increases exponentially with P%. Values of ρPS as high as 1 × 109 Ω cm at room temperature were obtained once P% exceeds 60%. ρPS was found to be thermally activated, in particular, when the temperature increases from 30 to 200 °C, a decrease of three decades is observed on ρPS. Based on these results, it was also possible to deduce the carrier transport mechanisms in PS. For P% lower than 45%, the conduction occurs through band tails and deep levels in the tissue surrounding the crystallites. When P% overpasses 45%, electrons at energy levels close to the Fermi level allow a hopping conduction from crystallite to crystallite to appear. This study confirms the potential of PS as an insulating material for applications such as power e...
14 citations
Patent•
23 May 2013TL;DR: In this article, a vertical power component including a silicon substrate of a first conductivity type, a lower surface of the substrate supporting a single electrode, and an upper region of the second conductivity Type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
14 citations
TL;DR: In this paper, the epitaxial growth of Ge virtual substrates directly on Si (001) and on different porosity porous silicon (pSi) buffers has been investigated, and the results indicate that Ge grown on low porosity (22%) pSi buffer has a better crystalline quality compared to Ge growing on bulk Si and on higher porosity buffers.
Abstract: We report on the epitaxial growth of Ge virtual substrates directly on Si (001) and on different porosity porous silicon (pSi) buffers. Obtained results indicate that Ge grown on low porosity (22%) pSi buffer has a better crystalline quality compared to Ge grown on bulk Si and on higher porosity buffers. This result is attributed to the compliant nature of pSi and to its reduced Young's modulus, which leads to plastic tensile deformation of the 22% porosity buffer under the in-plane tensile stress introduced by Ge lattice. The same result is not observed for higher porosity buffers, this effect being attributed to the higher buffer fragility. A low porosity pSi layer can hence be used as buffer for the growth of Ge on Si virtual substrates with reduced dislocation content and for the growth of Ge based devices or the successive integration of III-V semiconductors on Si.
10 citations
TL;DR: In this paper, the structural, optical and thermal properties of n-type (100), p-type(100), and (111) mesoporous silicon (MePSi) are reported.
Abstract: In this paper, the structural, optical and thermal properties of n-type (100),
p-type (100) and (111) mesoporous silicon (MePSi) are reported. The mesoporous silicon was
prepared by an electrochemical process from bulk silicon wafer. Depending on the etching
depth, analyses show that the porosity of p-type (111) increased by 32 to 40% compared to p
(100) which, in turn, increased by 22 to 48% compared to n-type (100). The structure
morphology and the abundance of Si-Ox and Si-Hy also depended heavily on the type and
crystal orientation of MePSi. The thermal properties of the MePSi layers such as thermal
conductivity (κ), volumetric heat capacity (ρCp) and thermal contact resistance (Rth) were
determined using the pulsed photothermal method. The thermal conductivity of bulk silicon
dropped sharply after etching, decreasing by more than twenty-fold in the case of n-type (100)
and by over forty-five fold for p-type (100) and (111). According to the percolation model
depending on both porosity and phonon confinement, the drop in thermal conductivity was
mainly due to the nanostructure formation after etching. Thermal investigations showed that
the volumetric heat capacity (ρCp) followed the barycentric model which depends mainly on
the porosity. The thermal contact resistances of MePSi layers were estimated to be in the
range of 1x10-8 to 1x10-7 K⋅m2⋅W-1.
8 citations
References
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05 Sep 2008
TL;DR: In this article, the fundamental physics of power semiconductor devices are discussed and an analytical model for explaining the operation of all power Semiconductor devices is presented, focusing on silicon devices.
Abstract: Fundamentals of Power Semiconductor Devices provides an in-depth treatment of the physics of operation of power semiconductor devices that are commonly used by the power electronics industry. Analytical models for explaining the operation of all power semiconductor devices are shown. The treatment focuses on silicon devicesandincludes the unique attributes and design requirements for emerging silicon carbide devices.
1,730 citations
TL;DR: In this article, all manifestations of pores in silicon are reviewed and discussed with respect to possible applications, with particular emphasis on macropores, which are classified in detail and reviewed in the context of pore formation models.
Abstract: All manifestations of pores in silicon are reviewed and discussed with respect to possible applications. Particular emphasis is put on macropores, which are classified in detail and reviewed in the context of pore formation models. Applications of macro-, meso-, and micropores are discussed separately together with some consideration of specific experimental topics. A brief discussion of a stochastic model of Si electrochemistry that was found useful in guiding experimental design for specific pore formation concludes the paper.
749 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...Background Up to now, porous silicon is widely investigated for sensing, photonic, or MEMS applications as it is well summarized in [1], but its mesoporous or microporous electrical properties are not massively exploited....
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TL;DR: In this paper, the mesopore morphology and its dependence on formation parameters, such as HF concentration, current density, bias, and substrate doping density, is investigated in detail.
Abstract: Electrochemical pore formation in silicon electrodes is a well-known phenomenon. While micropore formation is commonly understood as due to quantum size effects, the formation of larger pores is dominated by the electric field of the space charge region. In contrast to the macropore regime which is well understood, little is known about the morphology and formation mechanism of mesopores. In this report mesopore morphology and its dependence on formation parameters, such as HF concentration, current density, bias, and substrate doping density, is investigated in detail. In addition, a simulation of the breakdown conditions at the pore tip is performed which shows that mesopore formation is dominated by charge carrier tunneling, while avalanche breakdown is found to be responsible for the formation of large etchpits.
357 citations
"Non-oxidized porous silicon-based p..." refers background or result in this paper
...This typical morphology is coherent with observations presented in [11,12]....
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...The physical properties of the porous silicon layer depend on the doping profile from which it is formed [11]....
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...Based on [11], we may expect the formation of mesoporous and microporous layers, respectively, from the Piso and Pbase diffusions even if in our case, the doping profiles are not homogeneous, as usually reported, but gradual....
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TL;DR: In this paper, the effects of silicon dopant type, resistivity, current density, and hydrofluoric acid concentration on the formation and properties of porous silicon were investigated using cross-section transmission electron microscopy.
Abstract: A systematic study is presented of the effects of silicon dopant type, resistivity, current density, and hydrofluoric acid concentration on the formation and properties of porous silicon. Cross‐section transmission electron microscopy revealed the presence of two distinct microstructures. The structure formed is determined by the doping level with the transition occurring near degeneracy. A model of the anodisation process is presented which is based on the semiconducting properties of the material and which explains the formation of the two different types of porous structure observed.
234 citations
"Non-oxidized porous silicon-based p..." refers result in this paper
...This typical morphology is coherent with observations presented in [11,12]....
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TL;DR: The frequency dependence of the conductivity and the dielectric constant of various samples of porous Si in the regime 1 Hz-100 kHz at different temperatures is measured, in terms of activated hopping in a fractal network.
Abstract: We have measured the frequency dependence of the conductivity and the dielectric constant of various samples of porous Si in the regime 1 Hz-100 kHz at different temperatures. The conductivity data exhibit a strong frequency dependence. When normalized to the dc conductivity, our data obey a universal scaling law, with a well-defined crossover, in which the real part of the conductivity sigma' changes from an sqrt(omega) dependence to being proportional to omega. We explain this in terms of activated hopping in a fractal network. The low-frequency regime is governed by the fractal properties of porous Si, whereas the high-frequency dispersion comes from a broad distribution of activation energies. Calculations using the effective-medium approximation for activated hopping on a percolating lattice give fair agreement with the data.
172 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...[24], the conduction in the PS layer is controlled by carrier hopping on the pore wall and/or between all the pores....
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