Non-oxidized porous silicon-based power AC switch peripheries
TL;DR: It seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles.
Abstract: We present in this paper a novel application of porous silicon (PS) for low-power alternating current (AC) switches such as triode alternating current devices (TRIACs) frequently used to control small appliances (fridge, vacuum cleaner, washing machine, coffee makers, etc.). More precisely, it seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device. Based on the technological aspects of the most commonly used AC switch peripheries physically responsible of the TRIAC blocking performances (leakage current and breakdown voltage), we suggest to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles. Then, we comment the voltage capability of practical samples emanating from the proposed architecture. Thanks to the characterization results of simple Al-PS-Si(P) structures, the experimental observations are interpreted, thus opening new outlooks in the field of AC switch peripheries.
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22 Jan 2016
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09 May 2016
TL;DR: In this article, the relationship between anodization conditions and resulting morphology is defined, and the authors demonstrate that by careful tuning structure, thickness and porosity, well-engineered nanostructured porous silicon enables controlling electronic insulation properties, which certainly broaden the design option of power device periphery.
Abstract: The tunable semi-insulating nature of nanostructured porous silicon gives rise to a potential application in semiconductor industry — power switch periphery. In this work, fabrication of nanostructured porous silicon by anodic etching is investigated. The relationship between anodization conditions and resulting morphology is defined. Our work demonstrates that, by careful tuning structure, thickness and porosity, well-engineered nanostructured porous silicon enables controlling electronic insulation properties, which certainly broaden the design option of power device periphery.
1 citations
Cites background from "Non-oxidized porous silicon-based p..."
...Refer to [4] for more details about experimental setup....
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...[4] has demonstrated that, by varying PS thickness and porosity, the resulting electric insulation properties of nanostructured PS can approach or even surpass conventionally used isolating material....
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TL;DR: In this paper, a new silicate glass passivation was studied on metal-dielectrics-semiconductor structures to characterize the reliability performances of TRIAC devices and the presence of mobile ions was identified in the glass affecting the reliability performance.
Patent•
17 Nov 2016TL;DR: In this article, a vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivities type on a lower surface of the substrate, and the first well is bordered at a component periphery with an insulating porous silicon ring.
Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.
09 May 2016
TL;DR: In this paper, the use of porous silicon in RF passive components, power devices and energy micro-sources is described, and several prototypes have been performed on large area wafers in the last 3 years.
Abstract: This paper describes the way porous silicon can be integrated in many microelectronic devices. We show recent prototypes that have been performed on large area wafers in the last 3 years. In particular, the use of porous silicon in RF passive components, power devices and energy micro-sources is described.
Cites background from "Non-oxidized porous silicon-based p..."
...For instance, the periphery of power devices (AC switches) can integrate PSi in order to increase the number of chips per surface area [3]....
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References
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05 Sep 2008
TL;DR: In this article, the fundamental physics of power semiconductor devices are discussed and an analytical model for explaining the operation of all power Semiconductor devices is presented, focusing on silicon devices.
Abstract: Fundamentals of Power Semiconductor Devices provides an in-depth treatment of the physics of operation of power semiconductor devices that are commonly used by the power electronics industry. Analytical models for explaining the operation of all power semiconductor devices are shown. The treatment focuses on silicon devicesandincludes the unique attributes and design requirements for emerging silicon carbide devices.
1,730 citations
TL;DR: In this article, all manifestations of pores in silicon are reviewed and discussed with respect to possible applications, with particular emphasis on macropores, which are classified in detail and reviewed in the context of pore formation models.
Abstract: All manifestations of pores in silicon are reviewed and discussed with respect to possible applications. Particular emphasis is put on macropores, which are classified in detail and reviewed in the context of pore formation models. Applications of macro-, meso-, and micropores are discussed separately together with some consideration of specific experimental topics. A brief discussion of a stochastic model of Si electrochemistry that was found useful in guiding experimental design for specific pore formation concludes the paper.
749 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...Background Up to now, porous silicon is widely investigated for sensing, photonic, or MEMS applications as it is well summarized in [1], but its mesoporous or microporous electrical properties are not massively exploited....
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TL;DR: In this paper, the mesopore morphology and its dependence on formation parameters, such as HF concentration, current density, bias, and substrate doping density, is investigated in detail.
Abstract: Electrochemical pore formation in silicon electrodes is a well-known phenomenon. While micropore formation is commonly understood as due to quantum size effects, the formation of larger pores is dominated by the electric field of the space charge region. In contrast to the macropore regime which is well understood, little is known about the morphology and formation mechanism of mesopores. In this report mesopore morphology and its dependence on formation parameters, such as HF concentration, current density, bias, and substrate doping density, is investigated in detail. In addition, a simulation of the breakdown conditions at the pore tip is performed which shows that mesopore formation is dominated by charge carrier tunneling, while avalanche breakdown is found to be responsible for the formation of large etchpits.
357 citations
"Non-oxidized porous silicon-based p..." refers background or result in this paper
...This typical morphology is coherent with observations presented in [11,12]....
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...The physical properties of the porous silicon layer depend on the doping profile from which it is formed [11]....
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...Based on [11], we may expect the formation of mesoporous and microporous layers, respectively, from the Piso and Pbase diffusions even if in our case, the doping profiles are not homogeneous, as usually reported, but gradual....
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TL;DR: In this paper, the effects of silicon dopant type, resistivity, current density, and hydrofluoric acid concentration on the formation and properties of porous silicon were investigated using cross-section transmission electron microscopy.
Abstract: A systematic study is presented of the effects of silicon dopant type, resistivity, current density, and hydrofluoric acid concentration on the formation and properties of porous silicon. Cross‐section transmission electron microscopy revealed the presence of two distinct microstructures. The structure formed is determined by the doping level with the transition occurring near degeneracy. A model of the anodisation process is presented which is based on the semiconducting properties of the material and which explains the formation of the two different types of porous structure observed.
234 citations
"Non-oxidized porous silicon-based p..." refers result in this paper
...This typical morphology is coherent with observations presented in [11,12]....
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TL;DR: The frequency dependence of the conductivity and the dielectric constant of various samples of porous Si in the regime 1 Hz-100 kHz at different temperatures is measured, in terms of activated hopping in a fractal network.
Abstract: We have measured the frequency dependence of the conductivity and the dielectric constant of various samples of porous Si in the regime 1 Hz-100 kHz at different temperatures. The conductivity data exhibit a strong frequency dependence. When normalized to the dc conductivity, our data obey a universal scaling law, with a well-defined crossover, in which the real part of the conductivity sigma' changes from an sqrt(omega) dependence to being proportional to omega. We explain this in terms of activated hopping in a fractal network. The low-frequency regime is governed by the fractal properties of porous Si, whereas the high-frequency dispersion comes from a broad distribution of activation energies. Calculations using the effective-medium approximation for activated hopping on a percolating lattice give fair agreement with the data.
172 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...[24], the conduction in the PS layer is controlled by carrier hopping on the pore wall and/or between all the pores....
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