Non-oxidized porous silicon-based power AC switch peripheries
TL;DR: It seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles.
Abstract: We present in this paper a novel application of porous silicon (PS) for low-power alternating current (AC) switches such as triode alternating current devices (TRIACs) frequently used to control small appliances (fridge, vacuum cleaner, washing machine, coffee makers, etc.). More precisely, it seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device. Based on the technological aspects of the most commonly used AC switch peripheries physically responsible of the TRIAC blocking performances (leakage current and breakdown voltage), we suggest to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles. Then, we comment the voltage capability of practical samples emanating from the proposed architecture. Thanks to the characterization results of simple Al-PS-Si(P) structures, the experimental observations are interpreted, thus opening new outlooks in the field of AC switch peripheries.
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TL;DR: In this article, the authors present all the possible porous silicon substrates, which can be used for RF devices, and the intrinsic electrical properties of porous silicon such as AC electrical conductivity or dielectric constant are also detailed.
Abstract: The increasing expansion of telecommunication applications leads to the integration of complete system-on-chip associating analog and digital processing units. Besides, the passive elements occupy an increasing silicon footprint, compromising circuit scalability and cost. Moreover, passive components’ performances are limited by the proximity of lossy Si substrate and surrounding metallization. Then, obviously, the characteristics of the substrate become crucial for monolithic radio frequency (RF) systems to reach high performances. So, looking for integrated circuit compatible processes, porous silicon (PS) seems to be a promising candidate as it can provide localized isolating regions from various silicon substrates. In this review, we first present all the possible porous silicon substrates, which can be used for RF devices. In particular, we put the emphasis on the etching conditions, leading to high thickness localized PS layers. The intrinsic electrical properties of porous silicon such as AC electrical conductivity or dielectric constant are also detailed, and the results extracted from the literature are commented. Then, we describe the performances of widespread RF devices, that is, inductors or coplanar waveguides. Finally, we describe methodologies used for predicting RF electrical responses of PS isolated devices, based on electromagnetic simulations.
38 citations
TL;DR: In this paper, the porosity of porous silicon (PS) was found to be the major contributor to the PS resistivity (ρPS), and ρPS increases exponentially with P%.
Abstract: The resistivity of p type porous silicon (PS) is reported on a wide range of PS physical properties. Al/PS/Si/Al structures were used and a rigorous experimental protocol was followed. The PS porosity (P%) was found to be the major contributor to the PS resistivity (ρPS). ρPS increases exponentially with P%. Values of ρPS as high as 1 × 109 Ω cm at room temperature were obtained once P% exceeds 60%. ρPS was found to be thermally activated, in particular, when the temperature increases from 30 to 200 °C, a decrease of three decades is observed on ρPS. Based on these results, it was also possible to deduce the carrier transport mechanisms in PS. For P% lower than 45%, the conduction occurs through band tails and deep levels in the tissue surrounding the crystallites. When P% overpasses 45%, electrons at energy levels close to the Fermi level allow a hopping conduction from crystallite to crystallite to appear. This study confirms the potential of PS as an insulating material for applications such as power e...
14 citations
Patent•
23 May 2013TL;DR: In this article, a vertical power component including a silicon substrate of a first conductivity type, a lower surface of the substrate supporting a single electrode, and an upper region of the second conductivity Type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
14 citations
TL;DR: In this paper, the epitaxial growth of Ge virtual substrates directly on Si (001) and on different porosity porous silicon (pSi) buffers has been investigated, and the results indicate that Ge grown on low porosity (22%) pSi buffer has a better crystalline quality compared to Ge growing on bulk Si and on higher porosity buffers.
Abstract: We report on the epitaxial growth of Ge virtual substrates directly on Si (001) and on different porosity porous silicon (pSi) buffers. Obtained results indicate that Ge grown on low porosity (22%) pSi buffer has a better crystalline quality compared to Ge grown on bulk Si and on higher porosity buffers. This result is attributed to the compliant nature of pSi and to its reduced Young's modulus, which leads to plastic tensile deformation of the 22% porosity buffer under the in-plane tensile stress introduced by Ge lattice. The same result is not observed for higher porosity buffers, this effect being attributed to the higher buffer fragility. A low porosity pSi layer can hence be used as buffer for the growth of Ge on Si virtual substrates with reduced dislocation content and for the growth of Ge based devices or the successive integration of III-V semiconductors on Si.
10 citations
TL;DR: In this paper, the structural, optical and thermal properties of n-type (100), p-type(100), and (111) mesoporous silicon (MePSi) are reported.
Abstract: In this paper, the structural, optical and thermal properties of n-type (100),
p-type (100) and (111) mesoporous silicon (MePSi) are reported. The mesoporous silicon was
prepared by an electrochemical process from bulk silicon wafer. Depending on the etching
depth, analyses show that the porosity of p-type (111) increased by 32 to 40% compared to p
(100) which, in turn, increased by 22 to 48% compared to n-type (100). The structure
morphology and the abundance of Si-Ox and Si-Hy also depended heavily on the type and
crystal orientation of MePSi. The thermal properties of the MePSi layers such as thermal
conductivity (κ), volumetric heat capacity (ρCp) and thermal contact resistance (Rth) were
determined using the pulsed photothermal method. The thermal conductivity of bulk silicon
dropped sharply after etching, decreasing by more than twenty-fold in the case of n-type (100)
and by over forty-five fold for p-type (100) and (111). According to the percolation model
depending on both porosity and phonon confinement, the drop in thermal conductivity was
mainly due to the nanostructure formation after etching. Thermal investigations showed that
the volumetric heat capacity (ρCp) followed the barycentric model which depends mainly on
the porosity. The thermal contact resistances of MePSi layers were estimated to be in the
range of 1x10-8 to 1x10-7 K⋅m2⋅W-1.
8 citations
References
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TL;DR: The results suggest that a Poole-Frenkel type of mechanism accounts for the observed electric-field-enhanced conduction in porous Si layers prepared by anodic etching of two different kinds of (100) p-type Si substrates.
Abstract: We present a study of the electrical transport in porous Si layers prepared by anodic etching of two different kinds of (100) p-type Si substrates. It is shown that by choosing a sufficiently thick layer, the problem of injection from the contacts can be eliminated. In this way we measure the intrinsic transport properties. The results suggest that a Poole-Frenkel type of mechanism accounts for the observed electric-field-enhanced conduction.
170 citations
Additional excerpts
...[14] 100 5 HF (49%) + ethanol (1:1) 30 ? 3 to 5 0...
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TL;DR: In this paper, a new isolation technique for bipolar integrated circuits was proposed by making use of the properties of the film such that it can be formed several microns thick and oxidized easily to form an insulator.
Abstract: Preparation, properties, and applications of porous silicon film were investigated. Silicon single crystal is converted into porous silicon film by anodization in concentrated hydrofluoric acid at currents below the critical current density. When an n‐type silicon was anodized, the silicon surface was illuminated to generate holes which were necessary for this anodic reaction. The growth rate of the film, from n‐type silicon, was larger than that from p‐type silicon in this experimental condition. The crystalline structure was the same as that of silicon single crystal. A new isolation technique for bipolar integrated circuits was proposed by making use of the properties of the film such that it can be formed several microns thick and oxidized easily to form an insulator. The main feature of the technique is that it provides a means to form thick insulating film inlaid through the n‐type epitaxial layer without prolonged heat‐treatment. A preliminary experiment was carried out to test the practical usage of the technique.
149 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...Second, the isolation of silicon islands, where bipolar or MOS transistors may be integrated, has been studied in [3-5] for the development of a novel integrated circuit technology....
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TL;DR: In this article, a FIPOS/CMOS logic array with 1.3K gate is successfully fabricated, which shows a higher speed and lower power dissipation than the gates fabricated by bulk CMOS technology.
Abstract: Processing steps of FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's are presented, FIPOS technology realizes a silicon-on-insulator structure, utilizing thick porous oxidized silicon and donors produced by proton implantation. New processing steps are proposed which provides small surface step and are suitable for LSI fabrication. Formation conditions of thick porous oxidized silicon are established by density control technique for porous silicon using a newly developed anodization system. CMOS devices are fabricated in isolated silicon layers and it is shown that the characteristics of n-channel and p-channel MOSFETS's are sufficient for application to CMOS LSI's. A FIPOS/CMOS logic array with 1.3K gate is successfully fabricated, which shows a higher speed and lower power dissipation than the gates fabricated by bulk CMOS technology. These results indicate that FIPOS technology is very useful for realizing high-performance CMOS LSI's.
120 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...Second, the isolation of silicon islands, where bipolar or MOS transistors may be integrated, has been studied in [3-5] for the development of a novel integrated circuit technology....
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TL;DR: In this paper, a new model for the charge transport mechanism based on constrictions of conductive pathways produced by charged surface traps is proposed and verified in experiments, and a decrease in conductivity is observed for micro and mesoporous silicon samples.
110 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...concentration and polarization on pore walls, carriers may flow through Si(P) channels as illustrated on Figure 8 [17,19,22]....
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TL;DR: In this paper, an aluminum-porous p+ silicon junction was used to demonstrate that dc current increases up to two orders of magnitude in the presence of ammonia, as for a series of various gases.
Abstract: Using an aluminum–porous p+ silicon junction, we have realized a sensor which dc current increases up to two orders of magnitude in the presence of ammonia, as for a series of various gases. To interpret quantitatively this phenomenon, we assume that the conductivity is governed by the width of a channel resulting from the partial depletion of silicon located between two pores. This depleted region is due to the charges trapped on surface states associated with the Si–SiO2 interface where SiO2 is the native silicon oxide. When some gas is adsorbed, mainly on Si–H bonds, we propose there is an electrical screening of the interface states (mainly dangling bonds located in the neighborhood of the Si–H bonds), leading to a decrease of the depleted region, i.e., an increase of the width of the channel and thus an increase of the current.
104 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...Stievenard and Deresmes [19] 100 0.01 HF (40...
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...Figure 8 Anderson model: conduction in columnar porous silicon layers with low porosities from [17,19]....
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...Stievenard D, Deresmes D: Are electrical properties of an aluminumporous silicon junction governed by dangling bonds?...
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...Among all listed studies in Table 1, the results of Balagurov et al. [15], Anderson et al. (low porosity part) [17], and Stievenard and Deresmes [19] seem to be described by the AN model....
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...concentration and polarization on pore walls, carriers may flow through Si(P) channels as illustrated on Figure 8 [17,19,22]....
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