Non-oxidized porous silicon-based power AC switch peripheries
TL;DR: It seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles.
Abstract: We present in this paper a novel application of porous silicon (PS) for low-power alternating current (AC) switches such as triode alternating current devices (TRIACs) frequently used to control small appliances (fridge, vacuum cleaner, washing machine, coffee makers, etc.). More precisely, it seems possible to benefit from the PS electrical insulation properties to ensure the OFF state of the device. Based on the technological aspects of the most commonly used AC switch peripheries physically responsible of the TRIAC blocking performances (leakage current and breakdown voltage), we suggest to isolate upper and lower junctions through the addition of a PS layer anodically etched from existing AC switch diffusion profiles. Then, we comment the voltage capability of practical samples emanating from the proposed architecture. Thanks to the characterization results of simple Al-PS-Si(P) structures, the experimental observations are interpreted, thus opening new outlooks in the field of AC switch peripheries.
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TL;DR: In this article, the authors present all the possible porous silicon substrates, which can be used for RF devices, and the intrinsic electrical properties of porous silicon such as AC electrical conductivity or dielectric constant are also detailed.
Abstract: The increasing expansion of telecommunication applications leads to the integration of complete system-on-chip associating analog and digital processing units. Besides, the passive elements occupy an increasing silicon footprint, compromising circuit scalability and cost. Moreover, passive components’ performances are limited by the proximity of lossy Si substrate and surrounding metallization. Then, obviously, the characteristics of the substrate become crucial for monolithic radio frequency (RF) systems to reach high performances. So, looking for integrated circuit compatible processes, porous silicon (PS) seems to be a promising candidate as it can provide localized isolating regions from various silicon substrates. In this review, we first present all the possible porous silicon substrates, which can be used for RF devices. In particular, we put the emphasis on the etching conditions, leading to high thickness localized PS layers. The intrinsic electrical properties of porous silicon such as AC electrical conductivity or dielectric constant are also detailed, and the results extracted from the literature are commented. Then, we describe the performances of widespread RF devices, that is, inductors or coplanar waveguides. Finally, we describe methodologies used for predicting RF electrical responses of PS isolated devices, based on electromagnetic simulations.
38 citations
TL;DR: In this paper, the porosity of porous silicon (PS) was found to be the major contributor to the PS resistivity (ρPS), and ρPS increases exponentially with P%.
Abstract: The resistivity of p type porous silicon (PS) is reported on a wide range of PS physical properties. Al/PS/Si/Al structures were used and a rigorous experimental protocol was followed. The PS porosity (P%) was found to be the major contributor to the PS resistivity (ρPS). ρPS increases exponentially with P%. Values of ρPS as high as 1 × 109 Ω cm at room temperature were obtained once P% exceeds 60%. ρPS was found to be thermally activated, in particular, when the temperature increases from 30 to 200 °C, a decrease of three decades is observed on ρPS. Based on these results, it was also possible to deduce the carrier transport mechanisms in PS. For P% lower than 45%, the conduction occurs through band tails and deep levels in the tissue surrounding the crystallites. When P% overpasses 45%, electrons at energy levels close to the Fermi level allow a hopping conduction from crystallite to crystallite to appear. This study confirms the potential of PS as an insulating material for applications such as power e...
14 citations
Patent•
23 May 2013TL;DR: In this article, a vertical power component including a silicon substrate of a first conductivity type, a lower surface of the substrate supporting a single electrode, and an upper region of the second conductivity Type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.
14 citations
TL;DR: In this paper, the epitaxial growth of Ge virtual substrates directly on Si (001) and on different porosity porous silicon (pSi) buffers has been investigated, and the results indicate that Ge grown on low porosity (22%) pSi buffer has a better crystalline quality compared to Ge growing on bulk Si and on higher porosity buffers.
Abstract: We report on the epitaxial growth of Ge virtual substrates directly on Si (001) and on different porosity porous silicon (pSi) buffers. Obtained results indicate that Ge grown on low porosity (22%) pSi buffer has a better crystalline quality compared to Ge grown on bulk Si and on higher porosity buffers. This result is attributed to the compliant nature of pSi and to its reduced Young's modulus, which leads to plastic tensile deformation of the 22% porosity buffer under the in-plane tensile stress introduced by Ge lattice. The same result is not observed for higher porosity buffers, this effect being attributed to the higher buffer fragility. A low porosity pSi layer can hence be used as buffer for the growth of Ge on Si virtual substrates with reduced dislocation content and for the growth of Ge based devices or the successive integration of III-V semiconductors on Si.
10 citations
TL;DR: In this paper, the structural, optical and thermal properties of n-type (100), p-type(100), and (111) mesoporous silicon (MePSi) are reported.
Abstract: In this paper, the structural, optical and thermal properties of n-type (100),
p-type (100) and (111) mesoporous silicon (MePSi) are reported. The mesoporous silicon was
prepared by an electrochemical process from bulk silicon wafer. Depending on the etching
depth, analyses show that the porosity of p-type (111) increased by 32 to 40% compared to p
(100) which, in turn, increased by 22 to 48% compared to n-type (100). The structure
morphology and the abundance of Si-Ox and Si-Hy also depended heavily on the type and
crystal orientation of MePSi. The thermal properties of the MePSi layers such as thermal
conductivity (κ), volumetric heat capacity (ρCp) and thermal contact resistance (Rth) were
determined using the pulsed photothermal method. The thermal conductivity of bulk silicon
dropped sharply after etching, decreasing by more than twenty-fold in the case of n-type (100)
and by over forty-five fold for p-type (100) and (111). According to the percolation model
depending on both porosity and phonon confinement, the drop in thermal conductivity was
mainly due to the nanostructure formation after etching. Thermal investigations showed that
the volumetric heat capacity (ρCp) followed the barycentric model which depends mainly on
the porosity. The thermal contact resistances of MePSi layers were estimated to be in the
range of 1x10-8 to 1x10-7 K⋅m2⋅W-1.
8 citations
References
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TL;DR: In this paper, it was shown that the common interpretation of the currentvoltage characteristics, which assumes that the current is limited by the Schottky barrier at the metal-porous Si interface, is wrong.
Abstract: The current‐voltage characteristics and the photoresponse of metal‐porous Si–p‐type Si heterostructures have been studied. It is shown that the common interpretation of the current‐voltage characteristics, which assumes that the current is limited by the Schottky barrier at the metal‐porous Si interface, is wrong. An alternative explanation based on the electric‐field dependence of the porous Si conductivity is suggested. It is shown that the rectifying behavior originates from a depletion inside the c‐Si substrate at its interface to the porous Si.
102 citations
"Non-oxidized porous silicon-based p..." refers background or methods in this paper
...(BC) [21] are used to interpret all urrent is observed for PS thicknesses lower than 28 μm; not true in ambient er voltage....
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...We will call the first one ‘Anderson (AN)’ [17] and the second one ‘Ben-Chorin (BC)’ [21]....
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...This is possible because of the high density of states on pore walls, which pins the Fermi level at this interface as illustrated by the band diagram of Figure 9a [21]....
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98 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...Figure 8 Anderson model: conduction in columnar porous silicon layers with low porosities from [17,19]....
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...We will call the first one ‘Anderson (AN)’ [17] and the second one ‘Ben-Chorin (BC)’ [21]....
[...]
...(low porosity part) [17], and Stievenard and Deresmes [19] seem to be described by the AN model....
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...concentration and polarization on pore walls, carriers may flow through Si(P) channels as illustrated on Figure 8 [17,19,22]....
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TL;DR: In this paper, the authors studied the current-voltage and impedance characteristics of a series of metal-porous silicon (PS) junctions, having a typical porosity of 30% and a layer thickness ranging from 1.5 to 30 μm.
Abstract: To analyze the carriers transport in metal–porous silicon (PS) junctions, we studied the current–voltage and impedance characteristics of a series of junctions, having a typical porosity of 30% and a layer thickness ranging from 1.5 to 30 μm. PS conductivity as a function of the annealing temperature showed two characteristic regions at 150 and 550°C where the conductivity abruptly increased by several orders of magnitude. These temperatures coincide with the temperature of dissociation of Si–H–B complexes and of hydrogen effusion. After short time rinsing of high temperature annealed PS in hydrofluoric acid its resistivity returned to the initial high value it had in the as-prepared state. These results imply that hydrogen plays a key role in determining the conduction properties of PS. We argue that the hydrogen present in PS in high concentration effectively passivates the boron doping atoms. As a result the space charge region that compensates surface charges significantly widens and becomes essentially larger than the silicon wires which leads to the high resistivity of PS. Current–voltage dependencies exhibit a region of space charge limited current, which allows for the determination of the energy distribution density of states in PS.
51 citations
01 Apr 1965
TL;DR: The theory of operation, construction, and electrical characteristics of a new family of silicon thyristors for use as bidirectional (ac) switches are discussed in this article, where the potential differences created by the flow of current in these paths determine, in turn, the lateral distribution of injected charge carriers within the device during triggering interval.
Abstract: The theory of operation, construction, and electrical characteristics of a new family of silicon thyristors for use as bidirectional (ac) switches are discussed. With these p-n-p-n devices, load current flow in either direction can be controlled by the application of a low voltage, low current pulse between a gate trigger terminal and one of the load current terminals. Blocking current and voltage characteristics are similar to those of a silicon-controlled rectifier (SCR); but unlike SCR's they can switch load current of either polarity. Devices have been made which, in the blocking state, will support several hundred volts with very little current flow; yet, when in the conducting state, will carry many amperes with a voltage drop of approximately a volt. Static power switching with these devices in such applications as lamp dimming, temperature controls, small motor speed controls, etc., appears to be particularly important. For triggering, these new devices depend on the manipulation of lateral current paths. The potential differences created by the flow of current in these paths determine, in turn, the lateral distribution of injected charge carriers within the device during the triggering interval. This paper presents an analysis of lateral biasing effects and the parameters which control them.
43 citations
"Non-oxidized porous silicon-based p..." refers background in this paper
...Because of the direct connection to the mains, the TRIAC is bidirectional in voltage and current [9,10]....
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TL;DR: In this article, the current injection into metal/porous Si/bulk Si diodes was investigated by transport and photoresponse measurements, and the diode current was determined by the space charge region at the porous Si/Bulk Si interface.
Abstract: The current injection into metal/porous Si/bulk Si diodes is investigated by transport and photoresponse measurements. Under low forward bias, the diode current is determined by the space charge region at the porous Si/bulk Si interface. The activation energy of the photovoltage shows that holes are injected into porous Si states which have little quantum confinement. This is discussed in terms of the confinement model for porous Si photoluminescence.
35 citations